在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

賴永諭

書上都有講哩...加油看看先....
! A: z# o7 {  U$ g應該不難找到哩...

jasonxilion

gain margin is not considered in pll design？
/ m+ w5 B9 M5 u! q, s5 Xi don't think so.
) `0 E3 N( u5 m( A9 gisn't it dealt with the stability?

kmchen3089

回復 #1 option318 的帖子
3 V( I( a7 o" x. n( C; m(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
2 L  `; l, r- D4 p* Z) Q% A pll ,且亦有unstability issue
(see Charge-pump phase lock loops paper by Gardner
; M8 B& v  k* U9 tIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
(2) loop BW is related to jitter (or phase noise) ,and locking time
7 n" y  p  {/ k6 p4 Z  o7 Tso you have to consider loop BW  from jitter & locking time  spec
- g) ~, [! q3 H4 k& M(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
  ?, e) o. J1 W# n1 N4 ~, I8 B(4) In my opinion ,gain margin is not considered in pll design