在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
; e/ q( ~, V0 w2 Y% N/ ?否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
pll ,且亦有unstability issue
(see Charge-pump phase lock loops paper by Gardner
  G0 x% c9 e0 u: dIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
9 U' J" G4 v' c4 v9 r. _(2) loop BW is related to jitter (or phase noise) ,and locking time
so you have to consider loop BW  from jitter & locking time  spec
# d0 X1 u/ a/ k& D' J/ L, s(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
% f. W' Y3 y7 s4 T' N0 u+ Z/ s* ?- Wi don't think so.
isn't it dealt with the stability?

賴永諭

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