在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
% b; l( U, E9 H& N) e9 X pll ,且亦有unstability issue
8 F( q1 v5 ^2 x1 G5 ^* b(see Charge-pump phase lock loops paper by Gardner
) H1 b9 L- N# _; T2 Z( C0 {IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
% r- w/ s" \4 m(2) loop BW is related to jitter (or phase noise) ,and locking time
: W; u! }7 U9 u6 `, Y2 F/ Kso you have to consider loop BW  from jitter & locking time  spec
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
' [' I: \" D5 I& c1 V  G(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
0 S0 ?5 s$ e% I$ @. Yi don't think so.
" `: H' K$ d8 p0 ~isn't it dealt with the stability?

賴永諭

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