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Software Support " N& h' o# `3 _+ `
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i. 9 g( Y5 w6 c: S7 r! k- _+ D
9 V4 X6 }7 H7 D( d; o' l$ JPlatform Support
0 |3 V0 U: \2 b- Microsoft Windows XP (32 bit)
8 I2 W- g$ g0 h, v/ h; A
+ z: Z, K6 D( s4 CDevice Support , o8 o$ w( B2 D% {" h' D) e
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
8 ]7 u5 V2 a& t/ E7 W& |7 J9 D; |, t1 \. [
New Features
' E9 p H3 m4 JGeneral New Features and Changes : I( a ^2 x; G" r# R# {& R
- Supports "Create New Memory Part" for all the designs.
" i/ Y* L; Q7 @1 \8 D& v- DDR and DDR2 SDRAM designs for Spartan-3A.
6 \/ m7 [3 V( L( A- DDR SDRAM is supported for Virtex-5.
3 X. u9 ~" m9 X- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. , w9 X" I( \4 E
- MIG now pops up the design notes specific to the generated design.
% j1 q' i `+ U. b3 ~6 O- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. ( x [5 V# g4 C
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.
) `9 `1 U" R! Z+ t0 w- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
% a- W, r( r2 p( n( _+ c- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. # k: X% f1 f# T' f$ b
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". . H& b* O2 p* B- I9 [# q! J
- Default setting "DCI for Address and Control " is changed to "unChecked". 4 g- k) `* v% C- ]8 H% B* }
- Frequency slider is changed to editable box in the GUI.
5 q7 W4 K0 v' y- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
# j4 q w! \$ A$ V8 H- Removed console window when running MIG through CORE Generator. : E: S6 \8 T. F! @$ O/ S+ B% ]
- WASSO table (Set Advanced Options) accepts only numeric characters. + s0 _% c/ \9 i; o$ [5 a* j: b
- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. / G* ^/ C6 B. e \* ?9 g! Z
- Provided web links for all XAPPs in the docs folder of the designs. b% Q+ b$ H& N) M# a
- Provided link to Data Sheet instead of Log Sheet in the output window.
8 U+ m. ^# d. ^$ M3 i- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
* N$ F; ]% X+ B* ^( d& R- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank.
5 n9 K$ u# c/ E \! h- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
' n7 \) a: b# y6 r# ~1 e
. K$ n# | y! e, A0 kVirtex-5 New Features and Changes 4 _& R, F6 O- f$ `0 x3 Q; k
DDR2 SDRAM
1 R( v4 {, y$ O. u- New controller with several high-performance features. All the features are described in detail in the Application Notes. 0 K1 _8 Z& D! w' [4 C7 A
- Enhanced data calibration algorithms for higher reliability.
! C. ?. l9 p! V0 G- Bank Management feature is supported. 7 M% [. G4 _! X4 X
- Supports VHDL. 5 s: v I- k9 d7 G$ m) e
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
, H2 K6 h# z: V1 b- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
* C2 R- }. C) D* T( ~- M( {' Q3 g4 |- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. / A" e: p9 v2 A1 I! ?
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ! N/ G3 Y: M2 h
b. WASSO is applied to all the memory interface signals.
: |9 c' K( c: o% P$ A4 U% g! P2 S+ `c. Signals such as "Error" outputs are not part of the WASSO count.
+ }& g- S& U8 J) j. N2 n) o+ {' U' @
- R' m f' F; a( ZDDR SDRAM " \6 y+ G+ u+ P5 K9 e& O
- This is a new design for MIG. Supports Verilog and VHDL.
1 y4 ]! u+ ?+ h: X- w& }7 ]2 t- Bank Management feature is supported. 5 t. `) G" y# C0 q1 P
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. - b( s! A3 [; a" |
6 O3 i! O* c( c2 {+ t9 B+ M
QDRII SRAM % o8 Y: B9 Q; w
- Added support for VHDL. 2 }/ z4 D* q- d S7 i
- Added support for 72-bit designs.
" k0 s1 {, s. t/ Q$ w( H j; E- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
4 R& P; g4 \% V- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 # {$ t+ j; k. g
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. # v$ }& X0 b& I" O
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
/ |' H$ C. i& w) k6 m+ `' Ba. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. - R- z" l' X4 x" a9 ^) `
b. WASSO is applied to the output signals only. ' F! {, T) @* x& J7 M- K
$ |+ n1 t3 z) ~( ]
Virtex-4 New Features and Changes
, h' j; D% {) a; \, c1 EDDR2 SDRAM Direct Clocking
2 K U" m. T" Z- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
: Q4 a* e( W/ w" `. B: M- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.
: t8 J: b6 O3 `2 V4 }- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
& v- s5 D* E' t9 ?# c$ {- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. , ~- I+ L( O& ~7 E) h1 Q
- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. ; R, L3 t" H3 T/ l7 y; C j
- Removed all TIGs in UCF. The reset signal is now registered in every module.
$ s0 G" N! ~* }8 I5 k8 w4 W7 {- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ' b( L, J$ @/ h# m& L
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 1 X _& o. e, P+ Q& a
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- K' c' g- E& N4 L) k; J- Replaced `defines with localparams for Verilog.
" _6 i; k4 u0 ?! N! b& f6 ]- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 8 z, z9 n6 i. [$ w. F' w1 I
- Several state machines now use "One-Hot Encoding".
( D* G' y3 h k% x7 A- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. ; ^5 t" }( s6 y9 o9 \" c
- Signal INIT_DONE is brought to top module. % }; @8 M4 q% i* x! b9 |2 i3 f, L5 r
- Removed the UniSim primitive components declaration from VHDL modules. 7 |+ f8 g! e$ _$ _$ Y* u$ V
- We now support all multiples of 8-bit data widths even for x16 memory devices.
0 M! z* h: m. \7 t( Q4 a- We support memory devices of speed grades -3 and -667.
; D+ h0 `' n9 `1 I- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
! u& J" I- p- I- z, J: sa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
3 ]/ T1 D. ~' R8 ~' wb. WASSO is applied to all the memory interface signals. . [5 a2 x) Z, T$ q
c. Signals such as "Error" outputs are not part of the WASSO count.
' `: W T1 i3 {: _: p5 M7 N6 W2 A, H, E
DDR2 SDRAM SERDES Clocking
% s! B* Z5 X$ J7 I8 p( B5 P: r- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. 8 \% F* r' X7 K4 Z
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
7 ~% Y. e( S9 v# S/ i# B- Support for ODT. 4 w' H* }! n) C' B1 P; ]
- DQS# Enable is selectable from GUI through Mode registers.
. N# u- B, z' R6 P; O- Removed all TIGs in UCF. The reset signal is now registered in every module.
5 B k, i2 C9 S% N6 m0 t+ g- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ' F: z* P3 X/ y+ A
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 8 C" y- `4 u3 J& P& z8 J7 _$ M
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. * P9 Z) G* v6 \! b0 o& H
- Replaced `defines with localparams for Verilog. - g) e. d5 R% X9 y/ O" [$ [3 c
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 5 Y: Y l/ K& a$ r1 y8 o
- Removed the UniSim primitive components declaration from VHDL modules. ' m: e9 I# Q( g' d. N8 E' A
- We now support all multiples of 8-bit data widths even for x16 memory devices. & Y4 _: `0 `3 W! i1 U' `8 L7 K
- Signal INIT_COMPLETE is brought to top module.
~4 I N5 p8 r! X- b! j8 b- Memory devices of speed grades -5E and -40E are now supported.
, W% w1 L" B) d: z6 I- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. : [ V/ W( G' K! G
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
* o# e( M! F$ y/ q. X, vb. WASSO is applied to all the memory interface signals. 8 U- B. U( \9 a9 p; a) U( f! J& j% s
c. Signals such as "Error" outputs are not part of the WASSO count.
0 q j1 Q& x* I! P1 F* y/ z' Y7 T' R# E
7 l. p' z; I: |9 I. V' I7 @DDR SDRAM
6 p6 r3 r; l3 `7 ]- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
* ~: o& v$ \6 T5 w r1 i" B- Removed all TIGs in UCF. The reset signal is now registered in every module.
/ i; D6 j# j8 Y" t( a' ^- r% o d- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. + e9 r+ }' {3 a) r% F
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 0 k7 z2 c2 g3 L+ ], _) |
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
) `6 D* r" B/ A3 J' y: f; E- Replaced `defines with localparams for Verilog.
$ V! q! s4 ~; f2 g- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
# K6 Y: m4 c& g9 z! {- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 5 I# |+ Q5 C8 c1 c9 D
- Removed the UniSim primitive components declaration from VHDL modules.
* E$ e7 Z" E7 ]* L- We now support all multiples of 8-bit data widths even for x16 memory devices. ; [( i. H* v; s0 M$ X2 _0 o* i
- The signal "init_done" is now a port in the top module. + b0 s L$ H9 E N5 D
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 0 q) {1 o- W& z# S6 {
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
( O# U6 e6 k3 Qb. WASSO is applied to all the memory interface signals.
6 Q1 g N C M o# ?8 G7 Xc. Signals such as "Error" outputs are not part of the WASSO count.
) O6 }9 c; W. c8 n+ J9 b- E+ V# t1 b' g% l& l
RLDRAM II
- J0 |1 D7 \6 c" W/ C2 @- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
- X z8 b* y# ~! }1 ?" j& W- Removed all TIGs in UCF. The reset signal is now registered in every module.
" C2 x/ [8 ]' } C! _- The design now uses CLK0, instead of CLK50 and div16clk. 4 t, h) d- Z% h/ E D) R
- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
9 X7 N1 X8 h/ U- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. * z, Q: l- H9 [+ x
- Removed unused parameters from the parameter file.
+ O% A: k6 r# }& k- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 5 X' @9 k) \5 \* d4 |# @. g. c
- Replaced `defines with localparams for Verilog. 6 T9 m5 u6 ~( A4 ^
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
2 ~) q* {: g# N. u4 T6 _9 q- Removed the UniSim primitive components declaration from VHDL modules.
, ]3 L# V f4 D- The signal "INIT_DONE" is now a port in the top module.
1 K" \) y5 B" H$ @- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
; k H6 `6 Q( `# p* ]- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. ! I; v7 c0 L0 S6 S" l a
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
1 s5 n; u8 A, j' o5 J- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
" P N- L8 c! e1 I! }9 Ha. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 9 y A3 {% Y3 T$ u- [2 I9 Q+ i) _
b. WASSO count is applied on output signals only for SIO memory types. % A( r4 v( V6 P1 e& c8 C2 x, ?
c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.
7 |: m" D. g) ]5 G9 X
- {6 z' N/ c2 iQDRII SRAM . I8 ?$ K) N& Y" k) b. Q$ `
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
4 l% l8 y: a& b$ {, U' V- k/ j0 s- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic.
% r/ C3 c1 `# R/ p7 L- Supports generation of designs with out DCM.
* p: a' s( Y/ j+ J( J% N/ f6 L, v- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
% y! ~" o; E) m Y' h% H- Removed all TIGs in UCF. The reset signal is now registered in every module. & K: K9 r2 U' g9 ]6 n
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
' X( x! B/ o$ F8 x4 \% `- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
+ g; W& l) i$ ]& s! u- Replaced `defines with localparams for Verilog.
3 `4 S9 c% C3 M P- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
/ ]+ r/ q8 R" Q# ?( K% C- Removed the UniSim primitive components declaration from VHDL modules. 6 r+ {( P* K# u; J% m) e
- The signal "DLY_CAL_DONE" is now a port in the top module.
5 Z, n' K3 D: ]5 I c9 H1 q' Y- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 6 n( z8 t1 G# V( o. w1 C
- Added support for DDR Byte writes. " k* Y5 q L& V+ o
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. * v& \, V$ j# i; c* u; @
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. * l2 w$ V# z2 _% ]8 F8 H; v
b. WASSO is applied to the output signals only. 6 M5 o) x# q+ V
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. % W, Y5 G5 d' }- L4 X+ }0 `
7 x# o/ r0 s, I, h/ D: v) u2 P0 mDDRII SRAM & p% R4 e, C$ W0 r: Z0 h6 {% j; x% b
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
- I' N8 q% z7 Y0 `! Z5 u5 C, \- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. ! w: H, V& \2 J/ l6 Q/ R9 d4 P
- Supports generation of designs with out DCM.
4 @" O# }: i) Z& v3 Y" f; f- Part CY7C1526V18-250BZC has been removed from Memory Parts list.
( @7 y( ~0 A6 a' [ n3 a- Removed all TIGs in UCF. The reset signal is now registered in every module. . M( T6 g3 U! p8 E$ X
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. , y; ^) G! C% }) Z* o* E6 U
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. - n8 o% I" ]: j$ R
- Replaced `defines with localparams for Verilog. / u. F. O: `* w9 j& R
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
. \8 i, x g+ y1 Q: u! G" `( o$ W- Removed the UniSim primitive components declaration from VHDL modules. + I& r* P6 c( l3 G4 L( g
- The signal "DLY_CAL_DONE" is now a port in the top module.
8 M# C; t- \. @- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. $ j% \0 l) F& ?6 ?) S* n
- Added support for DDR Byte writes.
7 j- w! I3 }* W) M- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
# r, S& Y4 Y, |+ Ca. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 8 ~( M- Q9 J4 v
b. WASSO is applied to all the memory interface signals.
# `6 u1 r! s8 Q! o5 _5 r6 Nc. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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