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Software Support
+ ?* t+ f/ _0 l1 G$ y/ @1 Q- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i. : m$ B( e) j, W7 a
6 M: t6 q, J' n
Platform Support
: e& C* c ?6 c- Microsoft Windows XP (32 bit) # C9 H% @! I5 ?: ~( `
/ ?5 ^0 V3 \9 R, t* C
Device Support
8 [" w" A* F4 v5 y/ g- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. 8 h! M( x+ L6 v$ t' ~* s ~. R X
; R3 r& O5 [# n( z4 T2 W4 Q* a rNew Features # y7 _( [1 C4 D8 R6 X: R
General New Features and Changes
3 I8 ?; n' X* L& \# H; b5 I0 j/ P- Supports "Create New Memory Part" for all the designs.
: e" _# Y$ O; y9 ~4 ]) l% J; _% U- DDR and DDR2 SDRAM designs for Spartan-3A. & \4 E. m# ^ d0 L$ V7 N7 x. C
- DDR SDRAM is supported for Virtex-5.
4 e/ c5 G1 A. Z% j! M- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. ! E$ K* n' L2 T! ]* D( W) f
- MIG now pops up the design notes specific to the generated design.
) o; U, G+ V: \& `2 Q- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. : z- |3 r0 Z7 r5 v8 S" z
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. + H( d$ V% H; z" q9 A
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. 4 s6 B. ?0 v5 r
- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
1 a: w# J& E' H- E5 [& J- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". 1 M' l( ~3 l0 d9 V' v" T" N& o6 D
- Default setting "DCI for Address and Control " is changed to "unChecked". ]; M) x$ D5 @% l
- Frequency slider is changed to editable box in the GUI. 9 F" M0 I, P* a% r# U6 y1 p& B9 c
- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
; G! C: e1 s0 l0 {/ @/ ^# ~- Removed console window when running MIG through CORE Generator. 7 G: _/ q6 X2 r ~- w
- WASSO table (Set Advanced Options) accepts only numeric characters.
) U: |) {' K6 S o9 ~9 O- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
) H! C2 f4 i- n- Provided web links for all XAPPs in the docs folder of the designs. , D9 X" A, r0 J2 p
- Provided link to Data Sheet instead of Log Sheet in the output window.
! I3 G9 S! p+ `6 X- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. $ u3 Y7 n! L# D0 m
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. 7 r- Z; Q9 j& P; o" Q! V m
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. . S0 |+ N; u4 [7 c0 Y
# Q3 j; B, _" P" D+ T- x0 m( tVirtex-5 New Features and Changes
3 D2 K. x. f# \9 kDDR2 SDRAM , K" c9 [) ~. z( b8 X, {
- New controller with several high-performance features. All the features are described in detail in the Application Notes.
0 ]- Q/ R" Z& T: p$ J$ Z- Enhanced data calibration algorithms for higher reliability. 1 o* _) d0 N+ X: i! f4 v0 h
- Bank Management feature is supported. ! H+ c/ B" ]. a* x- n2 b
- Supports VHDL. / \+ @ J- q) T7 k. ?# R
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. 3 C: z9 H$ `6 | w
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. " A; s j8 k: Y; C" g5 ^0 R/ v/ S+ _! q
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions.
. i2 x: f6 d) Q6 Ra. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
2 g1 Y" J9 K4 Qb. WASSO is applied to all the memory interface signals.
& o; X% s0 r4 W% p5 w( L1 oc. Signals such as "Error" outputs are not part of the WASSO count. 4 l1 {; |, k: J2 I6 \
. a6 h7 M- C, S/ H: A
DDR SDRAM + k' W' U! i O' I4 j1 @
- This is a new design for MIG. Supports Verilog and VHDL.
4 D/ n5 @7 C. z$ _1 i! F% o, z0 O! c. k- Bank Management feature is supported.
7 b$ F) ` q9 e2 k! I" d& U l- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. / \. F2 R1 Z" @+ R
: Y' ]" \, K9 |# f/ {* [
QDRII SRAM
+ s; f" ~' x8 W1 P; }7 h8 i; Q% Y0 A- Added support for VHDL.
- V3 t. x3 x! y3 x1 M+ p. a- Added support for 72-bit designs. + V- |5 ]" p/ B9 ?$ Z S/ p8 a8 M& x
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
6 ]/ |9 k1 f+ i* A: u _& _- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 2 n$ \7 V" f+ f& L* w* h
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. 9 M5 G3 |# n: M$ D- F
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. " f$ x' s1 m) s+ G: D/ H0 P8 W" Z
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
3 y" o( z4 m3 U( y7 r' pb. WASSO is applied to the output signals only.
' ~" h! s9 c6 u2 w7 K9 @4 e$ u+ w
Virtex-4 New Features and Changes
- B9 p J' } X7 u UDDR2 SDRAM Direct Clocking 8 I+ i7 N' f v7 w& l9 o0 J8 J
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. ' |0 M4 p1 R* o1 `- o" X( P; ^
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. ) X& ^( J* M1 b; C
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
3 Q Q" B- @6 b3 [- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
2 ^; f- k$ I$ g- J4 w" {- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. 6 @! [! V3 A$ x% `" ^, v) N$ z
- Removed all TIGs in UCF. The reset signal is now registered in every module.
9 r3 |) u9 D8 y1 `- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
3 G% L3 Q. [+ T0 w) z- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. & Y& P& ^7 h/ f, c7 z' x; T( l
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. % D1 B& U- ]. J
- Replaced `defines with localparams for Verilog.
. [$ E* Q+ U( j' J8 M `+ k- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
' @4 p0 `2 U6 c; {' V- Several state machines now use "One-Hot Encoding". / L+ |; b2 J4 n/ W; W0 I4 L! Z. ^
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. " G9 G3 q9 C6 j* s5 L& \, q; k U
- Signal INIT_DONE is brought to top module. , l1 V7 e J. V% J0 f
- Removed the UniSim primitive components declaration from VHDL modules. * ^5 J% `4 }5 c% _) a. H" ^9 l
- We now support all multiples of 8-bit data widths even for x16 memory devices.
+ |) ]" V$ y/ ?; A- We support memory devices of speed grades -3 and -667.
8 C8 O9 w" [8 _4 ?1 j8 F- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ! X/ e; |2 E1 Y7 P1 J2 d" ]
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. & O: {" b0 _ y3 j" D4 ]
b. WASSO is applied to all the memory interface signals. J8 s6 Q- O+ |+ R7 U
c. Signals such as "Error" outputs are not part of the WASSO count.
/ V& {* f1 H' @- b u
, f, ^6 i1 F" c3 W3 e8 SDDR2 SDRAM SERDES Clocking & f7 W% {. P4 }# U6 u
- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
8 |1 h/ \( g& S8 o- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. . Y) q6 b; k, ^. L
- Support for ODT.
- ^2 d' _* Q, n0 X4 P- DQS# Enable is selectable from GUI through Mode registers.
. b( L) v! J% j7 v. V- Removed all TIGs in UCF. The reset signal is now registered in every module.
" k5 l% c# K- t) C- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
. Q7 ]7 k' N! q# n# q0 ?- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. & p+ T! W) T! v; Q
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 5 e% I( E* K- L& e" z3 d
- Replaced `defines with localparams for Verilog. ) i1 p# ]& D T! R
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. / x1 [' ?! i6 ~6 `7 P. ]! o: i: j
- Removed the UniSim primitive components declaration from VHDL modules.
Z% j4 [ a& z9 U9 t- We now support all multiples of 8-bit data widths even for x16 memory devices. ) O: \" s9 P4 ?) u
- Signal INIT_COMPLETE is brought to top module. 4 q. ~: i- a; _/ S4 Y
- Memory devices of speed grades -5E and -40E are now supported.
( r. p8 x: z- R& z1 U) m- ^3 q- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
& Q/ ?2 ^! o" L3 s1 a1 \3 ia. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
* L& ]! i. C! `$ b! q. n6 ob. WASSO is applied to all the memory interface signals. ( Z9 k$ f7 W* Y) M
c. Signals such as "Error" outputs are not part of the WASSO count.
5 T- f' e B# b1 P
4 S6 e& c- |# oDDR SDRAM 7 a1 @% j6 `6 c2 L
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
! W- T# x6 l8 ?' O6 o- Removed all TIGs in UCF. The reset signal is now registered in every module. ! k( ]' V) C; H+ A) W! E" q
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
, R/ X; j( o5 Y: ]" s9 C: ]- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
! u( G9 C, j, n2 n- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 0 ]" }8 i) }) `
- Replaced `defines with localparams for Verilog. , K: O( X) A$ s% r+ Z' `' u
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
& s6 M0 Z& b& K$ l$ \4 U/ s- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
0 K2 N, N2 N6 d3 A7 A! N- Removed the UniSim primitive components declaration from VHDL modules.
- j( z4 E) J* U7 a- We now support all multiples of 8-bit data widths even for x16 memory devices.
3 y& v. g/ I0 V2 U8 X0 M- The signal "init_done" is now a port in the top module.
* z/ r4 x5 j6 f- e( }- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ( `6 M3 Y! m# [0 X ^
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
) U3 u4 `: O% \# S; vb. WASSO is applied to all the memory interface signals. 1 E/ k2 M ?1 N/ u
c. Signals such as "Error" outputs are not part of the WASSO count. % w/ [' v- z% w) T
' [- d t7 N+ [! o" Y8 O
RLDRAM II + ^8 ]: l0 B2 ~. a" Y" u- ]
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
0 o% ]0 I e5 e$ B ~- Removed all TIGs in UCF. The reset signal is now registered in every module. M8 [7 a$ h1 _ ~8 s6 c9 R8 L4 \
- The design now uses CLK0, instead of CLK50 and div16clk. . a3 v- w2 w$ }0 k
- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
* @0 `" b2 R+ p. U. G }- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
y8 l: @5 l9 M- @; `0 P- Removed unused parameters from the parameter file.
% q; f7 a; @. K1 s M2 @- k* Q- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 8 Z4 W8 O" ~) P1 }! A- U# @% s& Z4 L
- Replaced `defines with localparams for Verilog. 9 v' T5 g# _+ ?
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 6 l9 p" Y2 g0 B8 ~4 G
- Removed the UniSim primitive components declaration from VHDL modules.
, K% J+ ?- D- d* e- The signal "INIT_DONE" is now a port in the top module.
- h4 |9 D6 o9 C+ ?7 j5 `- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. / X2 o$ x" n% }: z/ \4 \
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. 3 l1 w2 J" i, {; W! Q% P, O
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
4 f( R3 w; ? d2 [; Y0 s- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
3 j3 h. X2 ~( o$ a3 oa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 8 W. s* O2 b- ~
b. WASSO count is applied on output signals only for SIO memory types.
/ Q$ g3 C+ Q j' \c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.
/ |8 d6 x7 N$ |, q/ @: \
' R2 A4 E0 v( K5 _% a$ c+ AQDRII SRAM
# w: e/ D' i! b# {) V! F- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
* V3 i) e7 j: s2 k, I% t1 [- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. + T1 q' @3 ^6 B: E% ]
- Supports generation of designs with out DCM.
$ t2 I, ~! f# Z% M2 \8 \- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
% [! R( R0 `0 p+ B$ w4 ~! p/ K- Removed all TIGs in UCF. The reset signal is now registered in every module.
8 R |# I! U: ]- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ' F3 `6 Q& x2 V: g4 d
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. + g6 X- C3 g2 y% R- P
- Replaced `defines with localparams for Verilog.
$ L/ o1 d1 T; \$ V! y8 o8 y* I- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
, j7 \3 o' Y1 W6 I- [+ Z- Removed the UniSim primitive components declaration from VHDL modules. 3 W: a5 H* V; J2 ?9 L
- The signal "DLY_CAL_DONE" is now a port in the top module. 2 r& ~' C5 N0 [ p
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. I: p" n0 L; U; v' ]5 |" O
- Added support for DDR Byte writes.
: r. ?9 [8 j6 n5 _( J* a- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. + D/ v+ C) x- m6 P. P4 _9 Q# }
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
2 n$ l% V# ]' S, q- M6 h' }b. WASSO is applied to the output signals only.
" e8 l/ m. [5 `( h( d, pc. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.
0 F1 s1 E3 L) t z2 d6 q2 z# g; t4 Q; I9 H
DDRII SRAM
9 d9 h' o! B, W, r2 {0 x$ d- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 7 U4 Y/ a4 G V' @, [
- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. : _$ V, A t) a" T4 A
- Supports generation of designs with out DCM. , z' i& [4 C$ H* g
- Part CY7C1526V18-250BZC has been removed from Memory Parts list. 3 ?: Y8 `: U1 e( P5 @9 `, b; _4 S1 R
- Removed all TIGs in UCF. The reset signal is now registered in every module. 6 E- L: t, D3 _2 u& c+ H: J3 E
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
& j4 J8 C9 p# }% |9 H" p- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
e/ M4 `& ^' O) g7 k& @, u; h- Replaced `defines with localparams for Verilog.
1 a* D5 [1 F# F2 Y- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. / }4 ]: w4 ? Q+ T9 i8 ^2 _
- Removed the UniSim primitive components declaration from VHDL modules.
6 }; y: [6 z: f+ d( O/ {+ [- The signal "DLY_CAL_DONE" is now a port in the top module. + j( H, k/ J7 [
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. $ _7 Y. N+ s( k6 ~: O7 m# H6 f
- Added support for DDR Byte writes. 3 l& H) ]) L w: Z
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
0 E1 v2 U0 Y) v: fa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
* o% V1 t9 k, i3 db. WASSO is applied to all the memory interface signals.
! g7 N! T: g1 t7 F1 \6 z: X0 \c. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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