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Software Support
# F! T. o h3 Q- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
0 h9 Z9 B. o3 w7 I) S& I; r- B; J) k- g+ Q; ]) u! ^
Platform Support 4 A& \6 p: K; o$ e) z# S. V. N
- Microsoft Windows XP (32 bit)
2 r' v% ]2 M3 f- u% r& @" d3 X( h/ X* k& W
Device Support # n: Y) Y$ L# \5 t/ X: P+ E
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
; A, C& h. Z0 h# V4 y" F4 ^3 Z8 O6 z% ^/ J3 w" U$ P
New Features B/ n: _5 W5 R6 S6 g/ W
General New Features and Changes ' ]( _! S1 b$ }# Q
- Supports "Create New Memory Part" for all the designs.
9 q# r4 Q7 B% _$ C) ?' b- DDR and DDR2 SDRAM designs for Spartan-3A. : b5 ]* S! j B0 e) h
- DDR SDRAM is supported for Virtex-5. : u# c& ]9 m( w$ n9 C9 y7 x3 W
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. , [% ]9 h# e4 [7 H6 F/ O6 D
- MIG now pops up the design notes specific to the generated design. + ?, v/ s" ]& D0 f, K7 f5 Y
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. 8 F' I! k2 c0 Y, s2 {
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. ( O& m/ k {( s3 x+ ?3 ]+ R$ l
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
1 _" |+ s- m& D, N; y/ W- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. 6 N3 u: X& P( \/ |2 k
- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". 8 x! U( P! Y+ x% Z# ~7 ~5 s
- Default setting "DCI for Address and Control " is changed to "unChecked".
4 s& A1 h. M4 p- Frequency slider is changed to editable box in the GUI. , j8 h7 w N) U" ]" ^; q
- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
5 X$ l2 F" `; |/ g. i4 N3 u- Removed console window when running MIG through CORE Generator.
& a( h1 c) F8 o# M+ p V! }" T- WASSO table (Set Advanced Options) accepts only numeric characters. 4 R* H% E& i0 ~3 N" R' a
- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. 2 _8 K2 }$ d2 s& M1 S- m
- Provided web links for all XAPPs in the docs folder of the designs.
$ C3 E8 @. V+ D ?" _- Provided link to Data Sheet instead of Log Sheet in the output window.
: z1 ]/ o; h# b5 C6 m( I' ^6 f- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window.
+ i- Q: A& q5 Y2 D* o4 O6 F- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. 0 w5 b6 Z3 P" b% E" Q
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
0 T3 A3 k, A* ^+ y. T
2 t+ C- i$ b" z; x9 VVirtex-5 New Features and Changes 6 V/ a$ J$ A+ o( Z
DDR2 SDRAM , l Q' D* \# L
- New controller with several high-performance features. All the features are described in detail in the Application Notes. 4 [+ W7 u: T3 Z0 {$ e% P7 C% ~# {
- Enhanced data calibration algorithms for higher reliability. ' E5 }1 Q8 p$ ]) q% P
- Bank Management feature is supported.
' Q- {; W+ w; ~8 [8 U; i- Supports VHDL. 6 R% D6 R/ t$ q; D# @( f
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. 4 b" ]3 V5 j8 H! t
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
: ]0 B r# s' m" y- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. 1 `2 z& v$ D4 o+ g
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 8 B" ?" m2 M& [+ b$ U1 _
b. WASSO is applied to all the memory interface signals. 5 |, i1 W$ `7 y M& h" t1 F
c. Signals such as "Error" outputs are not part of the WASSO count.
' c8 n* A T" Q& j* l
, S; ^- s& Q) qDDR SDRAM
2 C5 H0 q9 q- n- This is a new design for MIG. Supports Verilog and VHDL. & b! {8 K( v! w* a2 |) {+ r; k- {1 ?
- Bank Management feature is supported. 9 F% p# S# @' k$ u4 \0 p
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. & U, T1 |0 F2 D; g6 ~, u: P
% w0 e& d# C# r8 B
QDRII SRAM
: O$ M- i- l# a2 u; w1 B, t8 m- Added support for VHDL. * z3 b) G* P( l
- Added support for 72-bit designs. ! j' _, Y& ~! B, j$ x% M" \
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
' [9 g1 G( c1 ]3 h. Q) U* f1 a- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 ( K( ]9 ] F$ e& O
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
7 R U3 q$ K8 ^& a3 M- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. & t- D# ~2 h+ T# p
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
* o2 s/ A5 p) i9 }; I, cb. WASSO is applied to the output signals only. % Y! }9 a4 M5 T* j/ o7 H
6 M9 H' _% c4 R9 O2 DVirtex-4 New Features and Changes
E# F. I+ W* Z, TDDR2 SDRAM Direct Clocking
$ N! s) y3 d; v: `. Y& @- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. 2 w" k) e1 d9 D+ i( |( W7 R
- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. - }5 ?( P$ l0 t7 |
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. , a7 g! f: Y" ^$ z' Q' A
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
. ?3 u8 q5 c# l. k8 z1 ~- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. 5 ^, ~3 G6 }: |8 y) R
- Removed all TIGs in UCF. The reset signal is now registered in every module. ) o$ ^' f4 _9 d# O* h& W( V7 x
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 5 N4 l. [0 K( Z! _
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
+ p! Y p( S7 P- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. * ~' N b* i" z/ d% q
- Replaced `defines with localparams for Verilog.
- C+ Z1 i* r3 T( @7 g. V- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 0 J; i' g; Q h4 U! B- [; t% }" ^
- Several state machines now use "One-Hot Encoding". 9 O, O, N# B6 i. Y+ V1 S* K+ f# t
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
5 G6 f6 Q' g5 d- Signal INIT_DONE is brought to top module. 7 e, j& G6 s: J2 q r
- Removed the UniSim primitive components declaration from VHDL modules. ( k- m. q' d- ^; ?
- We now support all multiples of 8-bit data widths even for x16 memory devices.
+ S! g* Z$ z; R- n- We support memory devices of speed grades -3 and -667. 4 m8 V1 I# o; a R3 x6 c
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
; b% y4 Z7 b$ f; {, n0 u3 F1 K0 }# ya. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
/ \$ [, `! {! Q3 d& b! y# [b. WASSO is applied to all the memory interface signals. / u5 x, \7 s. H
c. Signals such as "Error" outputs are not part of the WASSO count.
3 f6 G6 A; A8 K/ v
- ~( {' O9 z( D: t) h! MDDR2 SDRAM SERDES Clocking
2 c+ R4 I! }! g X3 [- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. 7 y# m* x8 h0 H- Z$ w% z
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 9 ]8 f( l! V/ X( L
- Support for ODT.
6 y0 b. t& |8 E2 s- A* f, y- DQS# Enable is selectable from GUI through Mode registers.
, d5 I: r! N1 w5 R( y+ P0 j- Removed all TIGs in UCF. The reset signal is now registered in every module. 8 H( t4 M0 K" O9 x: v5 a
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 8 g9 Q" k/ H0 t7 d4 d# N+ b
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
" l1 E: F$ D/ r& r- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
" D# b* Y% Q+ B6 K- G* D: u' a+ q- Replaced `defines with localparams for Verilog. - t, t" {) L- u7 p% Y. K
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
: j8 M3 s: p; t4 j- Removed the UniSim primitive components declaration from VHDL modules. 6 c, z; H; L7 k7 o+ V
- We now support all multiples of 8-bit data widths even for x16 memory devices. 8 i' c4 Y# \ p4 v* R9 f; X" p( l' x; Y
- Signal INIT_COMPLETE is brought to top module.
6 b e0 O `& | ~- Memory devices of speed grades -5E and -40E are now supported. ' v: D9 s! K0 \0 r
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
' R" [1 d- G( a' y: @a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 0 U6 x* E, l5 T- H1 ?2 }
b. WASSO is applied to all the memory interface signals. 1 L$ i, x' h. X' f. ]
c. Signals such as "Error" outputs are not part of the WASSO count. 2 x1 N; W `4 K2 L) W4 b* L
3 }6 G. G% ?6 t: C
DDR SDRAM
( [# u% g2 V$ r* s4 o3 r4 [0 l: D# y! r- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
; B( h Q6 B- G0 P6 C4 t: }- Removed all TIGs in UCF. The reset signal is now registered in every module.
+ B7 G' g P, Y' v- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 8 J+ Y* F6 T" T$ r+ {- X% y
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 1 s" [# I' ~/ T1 u+ y& k0 X D
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
1 L# T$ j2 U2 ~: }/ H- Replaced `defines with localparams for Verilog. * F0 Z+ s9 r. H0 y+ N* p9 D8 o
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 6 _- Y% T8 f. o0 l+ ^& c4 J
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
+ R' D5 [2 d$ p( x! ~- Removed the UniSim primitive components declaration from VHDL modules.
8 e+ _) B7 O# m$ B& s9 J/ z$ {- We now support all multiples of 8-bit data widths even for x16 memory devices.
# r6 t1 Y, I* e* [. J- s& q- The signal "init_done" is now a port in the top module. ( w7 k7 b) K1 @2 W/ S+ G7 r6 I
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
# Z( |' h) \7 w1 x2 ~& Pa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 3 V# A. a! e5 T/ J* ^
b. WASSO is applied to all the memory interface signals. % t+ v" _( C/ u8 ?
c. Signals such as "Error" outputs are not part of the WASSO count.
( [' J/ m/ C. d& [ s( A( r
, R4 [1 |+ `" ARLDRAM II
, a# z/ Z/ n. s3 Y' Z* g/ i( k8 A- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
9 ^) X- `* Z6 @2 l' a- Removed all TIGs in UCF. The reset signal is now registered in every module.
1 P( ^9 w/ h8 \- i- The design now uses CLK0, instead of CLK50 and div16clk. 3 o5 m0 h. n- W# i+ a6 f* z
- CLK200 is changed to differential clocks in mem_interface_top module (Design top). / S- B. a1 ~ {; C& J5 X
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
- [1 E$ P" L- z+ ~4 K- Removed unused parameters from the parameter file.
0 g8 ]- j" G) h1 x# t" n. p- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. $ p- b8 S, B5 G& K
- Replaced `defines with localparams for Verilog. ' }6 J0 `: [6 \1 l, R
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. % Q& o6 U7 M. p5 d. h
- Removed the UniSim primitive components declaration from VHDL modules. - w, h! y% L# Z( r9 g9 |* y
- The signal "INIT_DONE" is now a port in the top module. 7 C; z# h" i B1 h
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
7 W! b/ y3 ~9 r- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets.
: t: { {# }1 N- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file. # u0 T1 b2 W/ W% ?* K [* ?6 m
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
' V, j. A6 ]7 Qa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
% l; e( |' Z5 g# \b. WASSO count is applied on output signals only for SIO memory types.
5 I; N) A6 z+ [, h% @8 @c. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. 0 S4 r h5 C7 k8 R1 w4 c0 C; F3 i
4 _ F8 Z: V/ R& T9 e4 XQDRII SRAM " D1 P1 ]' T% M E7 u/ Q
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. . v6 r7 [' {' C" s; Q: D$ H. s
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. - j9 Z2 ]& \7 {, H
- Supports generation of designs with out DCM.
( S! Z' Y* p$ N5 }8 Y- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. % X8 D* }1 _8 h" U, y% X
- Removed all TIGs in UCF. The reset signal is now registered in every module.
9 n6 |1 Z5 ^/ H5 B/ \ X3 v- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
% K* C! Y7 d0 I: t5 A- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ! Z" e9 R6 J6 C" r: A+ s+ O! _+ F
- Replaced `defines with localparams for Verilog.
$ C) c+ U. `! m$ x" R" [- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
; ]; E0 ^& Y8 _. n- X) r8 X5 _- Removed the UniSim primitive components declaration from VHDL modules.
3 l4 Q7 F% Y# B7 W: ]4 N1 Q/ o, T- The signal "DLY_CAL_DONE" is now a port in the top module. 2 N: w8 K( }) T' L% z
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 7 m. z) I/ F# }1 s
- Added support for DDR Byte writes.
) k9 @- l3 k. v4 C+ Y; x4 I- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
1 m( d1 r i1 ?# f* w. G$ f) fa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
& l& q" m, b1 R8 ~; O7 m+ Ob. WASSO is applied to the output signals only.
l2 ]! A8 T+ `" x7 uc. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. 8 M/ b( k/ ?& _6 g; m* L3 W
3 M# \% N8 w' p1 |! @" D% YDDRII SRAM " U$ ]9 u4 e# N3 S9 u5 H. @; e1 t! S
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
# v) e' q/ F4 b8 u- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. + ~+ h' U r0 T, P
- Supports generation of designs with out DCM. - H2 U3 w. |2 }
- Part CY7C1526V18-250BZC has been removed from Memory Parts list. % ]8 \8 F2 k! m$ ~- W2 Z# N4 Z9 v/ Q
- Removed all TIGs in UCF. The reset signal is now registered in every module.
% z+ c$ Y9 s) M6 k3 h, ]) h* J6 M5 H- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
& u& I5 u: d8 p2 L- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
; E9 k9 t' l7 c* r- Replaced `defines with localparams for Verilog. 7 T/ R6 s- p: W9 @
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 6 k& {/ u+ R) s0 l) \1 M
- Removed the UniSim primitive components declaration from VHDL modules. ' i6 c4 w* d7 h( ^9 K& X
- The signal "DLY_CAL_DONE" is now a port in the top module. * f8 N4 D; ~; g! Q! X
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 4 ?2 r$ M0 j6 Q
- Added support for DDR Byte writes.
. ?! E; d4 p' r7 b# L- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. , k2 i, I5 P1 o' F2 k7 f
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ' x0 j( b5 v) l
b. WASSO is applied to all the memory interface signals. 6 V2 F: X( _' s2 B: F; K: x C+ T
c. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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