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Software Support
, S% N& N/ R, D; L; r- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
; A- ?# [. d: E3 f, a6 t% X) [* I! }. e! E) `- R! ]
Platform Support P( a* b; h5 W
- Microsoft Windows XP (32 bit)
' u1 K. z4 Z8 [- R% q& [9 N6 ]; [' j/ d3 _3 c: e* v! o
Device Support
: L5 Q! r z* u, K' ?9 w- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. 0 _& X1 X" W) r! m3 f) \
" Y3 W% l$ d" l6 i
New Features
* `; j6 p) q r: ^" ?! _& J' w$ E' qGeneral New Features and Changes
- [6 d9 ~7 f/ _- Supports "Create New Memory Part" for all the designs.
0 M; U C- [/ e% a- Z- DDR and DDR2 SDRAM designs for Spartan-3A. 1 x4 g5 A8 ~5 i
- DDR SDRAM is supported for Virtex-5. M& P) [' |: s O! o' C4 q
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM.
' T7 I5 t1 X2 T l* G( E% ^* e) O- MIG now pops up the design notes specific to the generated design.
8 ~ \: L8 p, p: [- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. ! q. l* X/ L! p' _) |
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes.
% z* W! f( c6 k- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
" J. D* R; a6 u w- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
# U0 N) r4 v, W0 J2 V- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". B" M# F; R# J& t* Y$ `: Y! Y
- Default setting "DCI for Address and Control " is changed to "unChecked".
; \5 b; U. f, u5 z5 a o. ]- Frequency slider is changed to editable box in the GUI.
J$ M. X3 j/ Z, S k: Z- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names.
, ?: M9 k1 N. h8 D- Removed console window when running MIG through CORE Generator. # W0 T4 _' l% ?( {8 C, h+ w
- WASSO table (Set Advanced Options) accepts only numeric characters.
( ]4 E& `6 [; ]) c1 x5 J2 G- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32.
7 R f$ \( L. {! S/ ~- Provided web links for all XAPPs in the docs folder of the designs.
9 a+ U$ u& g( h$ z8 z. A- Provided link to Data Sheet instead of Log Sheet in the output window. . @" t1 j" _# g" Z, F1 X
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. 3 X+ B4 U; b+ |1 k& t# ]
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. & s! N5 {8 a1 p) B4 H
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. 8 r @ F' K2 o8 t' I2 H
2 l- M, ^& `5 PVirtex-5 New Features and Changes 4 Q5 H# H. j8 t- f5 p; {0 t$ ^1 h
DDR2 SDRAM - Y! j; X0 `8 ]" q3 k* H+ [0 @
- New controller with several high-performance features. All the features are described in detail in the Application Notes.
% a+ _4 q7 T6 J5 t( D- Enhanced data calibration algorithms for higher reliability. 7 `$ I z5 C5 t% ]- O
- Bank Management feature is supported.
; D0 I, O( E& a( t7 _: I' P$ W- Supports VHDL. 0 g0 V* _6 y& d5 d' v: D
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear.
$ @2 y! Z, ^) g- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
2 B6 R5 t' U8 F* I- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. $ [6 L( f0 c, w o1 S
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 7 W+ T, D3 _7 u/ u5 ?) R% t
b. WASSO is applied to all the memory interface signals. 5 ^0 \ ?' u" o5 k1 i
c. Signals such as "Error" outputs are not part of the WASSO count.
( M5 s0 s0 a# b3 h/ \# u7 i! ^5 ^! ~& E0 v) l1 X k
DDR SDRAM 2 [9 y8 i' s4 v
- This is a new design for MIG. Supports Verilog and VHDL.
( I1 i X6 }# n/ Y5 ^: ~- Bank Management feature is supported.
! ]$ h4 _$ D- @0 V0 p% `- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. 1 h9 R1 ?8 @& m6 B; p% S0 B
6 s0 ^3 E, I9 g- K8 DQDRII SRAM $ j! o+ W+ E; c/ x* L$ g
- Added support for VHDL.
9 C' Z7 r2 o9 ]- Added support for 72-bit designs. # t3 w7 z$ f* m7 F1 t7 V
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay.
- O- @" P. W" R- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 . R6 [: H7 Q. i5 c) z- l/ z
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. 8 x- N5 A: y( c' A* Z% |0 ?
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. - s; P4 h$ G1 R# e3 R- w
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 3 _) O' C! p" k9 k J6 w0 R
b. WASSO is applied to the output signals only. $ {; F4 t" v) h$ D a7 g1 l
8 y3 d5 t' H! ?6 {/ m# b5 P cVirtex-4 New Features and Changes
% J7 W( }9 Y0 J+ v n* S0 S5 @DDR2 SDRAM Direct Clocking
3 j% p6 }4 }% c9 B+ ^' [- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
0 u, s2 l4 ?6 N+ N5 l' c+ l- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. : I7 x+ e2 Q( N+ x
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
: |5 Z! E6 a7 H+ U- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
# e! B E6 j$ |4 h' j- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
; m. `7 U6 P4 D- Removed all TIGs in UCF. The reset signal is now registered in every module.
! @3 o! Z: m, i- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
6 d) D# B5 v# _- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
6 T$ y: r. b+ q0 N- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 9 O& [& [& j, i2 P2 P( N
- Replaced `defines with localparams for Verilog.
& ?4 H7 U0 [6 ]- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
# V; a9 z' R# Z- Several state machines now use "One-Hot Encoding".
- ?6 i+ C4 }: P0 d0 A2 H- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks.
8 r8 g6 F7 C- [' ]- Signal INIT_DONE is brought to top module. 5 Q$ X* I* w7 P+ p- }" Y
- Removed the UniSim primitive components declaration from VHDL modules.
$ {) d. P9 u1 t5 K) Q/ t7 }- We now support all multiples of 8-bit data widths even for x16 memory devices.
% w, C6 ^: ~. E- We support memory devices of speed grades -3 and -667. R8 _$ e4 B# U& T3 Z$ D! m7 f5 `; U
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ) |) {. j5 z# [+ z- i9 d4 E& d# j( M9 V
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
$ u6 ]; y8 }9 @# Y5 }b. WASSO is applied to all the memory interface signals. . W* M( n3 J% N2 E8 L" Y1 D
c. Signals such as "Error" outputs are not part of the WASSO count.
/ B; [& S. Y+ q4 H* h) J. k, W' b4 j( A/ r
DDR2 SDRAM SERDES Clocking
. Q8 |" S( ]: r/ n5 y! W9 j1 P3 _- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. 5 j- i) m: j8 K* O. P
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
8 R* d8 L: i5 m1 {* x) j6 m- Support for ODT.
" R. J8 H* c3 ^- DQS# Enable is selectable from GUI through Mode registers. 0 d% ?* E) Z8 M! Z3 b6 R4 D y
- Removed all TIGs in UCF. The reset signal is now registered in every module. ( v, K2 Q2 k/ r/ e X0 P% U
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. ' F" j5 ?) D# s) A
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
0 J9 P) o- Z' F0 ?# G; U- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 3 T5 O- @" k+ H: B
- Replaced `defines with localparams for Verilog. - h' {% A8 r% s2 o+ g: l. @8 v A3 B
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 8 D, d+ p P m% n& p" V
- Removed the UniSim primitive components declaration from VHDL modules. & ~( b+ _5 E* c3 N1 Q" M
- We now support all multiples of 8-bit data widths even for x16 memory devices.
" C& ~& [2 I$ p6 k/ y- Signal INIT_COMPLETE is brought to top module. # D4 _$ o$ t1 j6 \. D
- Memory devices of speed grades -5E and -40E are now supported.
0 c+ Y3 K; X( G+ @0 g- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 4 |, O) I6 a- Q9 w1 A
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
% K% y) F. U h7 ^3 B. ]: T" `; u# ib. WASSO is applied to all the memory interface signals. ' C% [% ^; o8 a
c. Signals such as "Error" outputs are not part of the WASSO count. $ m6 R$ H2 b! z- D8 f% ]
9 h- H( r* [8 e8 g; q
DDR SDRAM ) ]7 H* Y! [! D* @$ J5 r; W) ~9 o
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
5 \ C/ v* F6 y+ W' Y4 S* r/ R% D- Removed all TIGs in UCF. The reset signal is now registered in every module.
m, x% ]% R5 u- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
# j1 y9 B+ h* \- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 4 l% g6 t& x( K) W2 r+ p a) Q
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
* V* g% Q, Q5 C- Replaced `defines with localparams for Verilog. 8 V K. T8 P6 M M& Z! n" Q, _+ E3 ~
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 5 A! U& a8 }( b0 C. A- g( l
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
7 f2 I5 H" t* O' N6 q- r- Removed the UniSim primitive components declaration from VHDL modules. % r3 T4 ]8 a0 c. i9 p P
- We now support all multiples of 8-bit data widths even for x16 memory devices. - Q, j3 @! B! z9 ^& q$ s) P+ p
- The signal "init_done" is now a port in the top module. : p3 D# F0 p( N Y
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
- b- P7 {# \4 @; j; W- Ba. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. $ Q1 s5 q* g6 E6 D
b. WASSO is applied to all the memory interface signals. 2 U, V- M' Q: Z1 E) h' `/ S8 b6 A
c. Signals such as "Error" outputs are not part of the WASSO count. 7 c& ?& N5 z) [: s$ Q) i: s+ i
; O" D; e/ C& _) r" zRLDRAM II
6 ? m- n0 q3 _" d5 c7 w9 o- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. : h% ]- V) E+ R( P) a
- Removed all TIGs in UCF. The reset signal is now registered in every module.
3 l) L& x. o4 R. T# ]- The design now uses CLK0, instead of CLK50 and div16clk.
) L! @. W8 l+ p6 g/ Y- CLK200 is changed to differential clocks in mem_interface_top module (Design top). - m: v0 G' U Y
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal.
, w/ Z: W- Q' s2 q. T8 K" X- Removed unused parameters from the parameter file. * \9 V$ L+ X- f4 I9 A
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
2 y1 |6 J/ w, A" X3 G2 O% S- Replaced `defines with localparams for Verilog. & _ x! S: E$ ^- j" B
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
3 l, {! G0 J" Z& j0 m8 W- Removed the UniSim primitive components declaration from VHDL modules.
4 B! c. X* ]9 x- The signal "INIT_DONE" is now a port in the top module. " S2 E. e. L3 P" Y: v7 O, w- U
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. 6 u4 }& W3 i/ G
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. . D: F: Z0 q) ?8 I; V
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
- z" p2 i# f* ]) }1 n( k) k- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
4 b1 X# K7 V+ {( I3 G) aa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
' e- ~5 E+ \: y" z3 o( e9 Cb. WASSO count is applied on output signals only for SIO memory types.
R. Y0 H+ r9 x7 ~3 P7 y! wc. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. * @$ F# x: O s% t
. g2 R3 Y+ \; Y. M2 l6 C) @
QDRII SRAM
4 i) [( _ q! D4 t4 z/ p+ [% F- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 6 O+ U' t0 T( N: z
- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. - m8 O0 E) j& A
- Supports generation of designs with out DCM. 0 M& I7 d7 ]( E; m. t
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
/ _; T7 T! b" ^- Removed all TIGs in UCF. The reset signal is now registered in every module.
" k$ o& S9 k! k/ g- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
$ T9 t; r0 ]4 O+ P+ A( N L# Q- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. " o R+ R8 R) S; |6 b
- Replaced `defines with localparams for Verilog.
" x' L6 o: b) N- [2 z' L& e- k8 G2 o- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
* x; c: {; N9 t7 x- Removed the UniSim primitive components declaration from VHDL modules. 0 l% p$ o1 k7 C3 @! ?- X
- The signal "DLY_CAL_DONE" is now a port in the top module.
2 @. d; D4 v$ V/ ?6 O% @+ V- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
: u' @: v5 U U" i- Added support for DDR Byte writes.
" i6 n$ k, t1 f! e( u" j3 O, G- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
5 g6 f+ }7 R8 i& _4 m: ]- f! ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. . o9 o2 _+ A1 a' w
b. WASSO is applied to the output signals only. & B& [3 g- e( Y5 m
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.
# S7 p. d+ n2 S. ~2 ]! N/ u
0 I8 }% |: ^% C; ^4 v5 MDDRII SRAM
8 y# Z) P" h/ F: e, g+ Z- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
$ M) f0 w* Z( O4 I- X- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. 8 U) B" G/ a# d0 R- j8 ^. R a5 r
- Supports generation of designs with out DCM.
7 P& d* n, _, ]7 ^7 b% S# g: W- Part CY7C1526V18-250BZC has been removed from Memory Parts list.
- m3 ?, \2 |4 x- Removed all TIGs in UCF. The reset signal is now registered in every module. 6 B, n( f* Q2 T* e4 X1 ~, o7 ]$ i7 m
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
- {( S, e, z! y1 l- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
+ c. c' v( ^9 T' E% x2 X# D- Replaced `defines with localparams for Verilog.
" U* L% D. C7 P+ B( X- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ' [3 e( X; g* u2 _, z5 s
- Removed the UniSim primitive components declaration from VHDL modules. . J& `3 S) k% y' y9 g8 @+ W6 I
- The signal "DLY_CAL_DONE" is now a port in the top module. 5 e5 d% q) o2 H1 y: _
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. 7 [. C- D, ?( Z4 l/ p% s
- Added support for DDR Byte writes.
! q; Q* J5 _. |( e# E7 q& L9 s- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ! b! q# h7 f" l! \' h1 T; o* _* g8 @; [
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 1 n* l8 @1 E5 H3 X9 S+ ~1 x
b. WASSO is applied to all the memory interface signals.
. s$ Z! G1 g" _$ z m \9 zc. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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