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回復 #1 tom218 的帖子
問題不夠清楚哦?????要VHDL還是Verilog??? 8bit的count有很多種,要up count還是down count?????要有加reset還是....????
b O0 T4 Q& Y我給你幾個參考.
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, l/ r& H u9 M$ }+ gVHDL count
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process (clock, reset) & Z8 P. U. d# M f
begin* T; I' l6 P) e* ~" ?; s: M
if reset='1' then : F: a" M' a; G
count <= (others => '0');
- x1 Z8 c$ R( P" \, K elsif clock='1' and clock'event then
# W7 Q5 s2 R2 i* w& \* g if clock_enable='1' then
5 R* \$ u' i5 }' a count <= count + 1;6 I- T$ h5 W; s: G/ T1 \
end if;
( ^5 c' C5 ^- ?+ e1 Q! f( w end if;* }& q1 C+ Y/ o( t9 @, {
end process;# s [- j7 [" c
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Verilog count! m( V H4 e* p- D8 U1 L- S
% b/ ]: v" I+ C, H2 creg [7:0] count;, ]1 n* l6 J8 x7 C( f2 k
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always @(posedge clk)6 j2 z! h0 }: j; L
if (clock_enable)1 s0 T1 c$ V: G
count <= count + 1; W2 J4 k3 O( |
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VHDL比較器& h3 \. S( C/ B8 [- }3 K; A8 J. r8 G" E
process(clock)- M4 z J- ~, O4 t, h3 D, K
begin
+ N2 w1 u0 H5 L6 I3 `' y if (clock'event and clock ='1') then
+ P$ S; T4 |0 F# r0 m- Z if ( input1 > input2 ) then 1 v) h+ |$ A1 l, }" }/ k
output <= '1';" L; z6 w/ b( u8 p- E9 ^ A
else
& n \& G- s- M6 l) B output <= '0';
+ E d. b: g% b, [: ?; { end if;5 r/ O0 `/ w8 M2 a
end if;
7 B4 K4 _2 x6 D: |5 w( hend process; / W* b9 s/ v. _# F, s: ~3 v: l; _
% R) }$ H7 M# }6 N' mprocess(clock)
' z- y3 I+ }4 R! y% o0 H% R5 s- j4 Nbegin+ x' D: p; N/ R: n5 H; n8 ?
if (clock'event and clock ='1') then 8 Z- ?1 `; C |9 ?. o$ X2 Q
if ( input1 < input2 ) then
0 Z( W* \* L5 \4 G5 X7 j output <= '1';' f2 I/ e% N8 a6 x% p0 e1 e/ ~
else
. [9 E5 c, _- Y output <= '0';
) D' p6 f. k4 b4 w7 P end if;2 h; o% O9 `# Y7 Q: d: }
end if; 4 c1 t0 W- A, ? \" x( ?, O
end process;
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Verilog比較器
! g# O6 G* X( Areg output;
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, Y" x8 p% O( B always @(posedge clock) L. e9 T: _3 ^6 a: G6 @6 e6 s
if (input1 > input2)
, v( }7 d( l" _' k$ y* _! W+ \ output <= 1'b1;" s+ n4 g4 R- m6 U! u9 A
else- g6 [! ~9 ~2 k: o3 {
output <= 1'b0;
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7 X$ ~" O( u* v6 h$ Dreg output;" v, W# F% p8 X5 k9 }
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always @(posedge clock)
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7 J0 A: I+ a3 g2 M, `- a' b* q/ j output <= 1'b1;
% p/ T8 L; u& l; U9 G1 J8 Z8 e else
6 u$ g! I6 U5 A Y# y: I6 m output <= 1'b0;
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希望有幫助^_^ |
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