Item( g8 D& j( @5 I6 y4 N: x% E
| SH77722 (SH-NaviJ2) Specifications% U' f2 P! b0 C; f I$ O
|
Type name) U: P+ f ?! q, n1 ` x& N- g) K
| R8A77722DA01BGV
2 a3 J5 w+ `' s5 |# [$ J | R8A77722DA02BGV
9 j3 q- q- B* e |
Power supply voltage
. K+ F+ Q# |- O @- A | 1.15 to 1.3 V (internal), * r/ |) V: y$ o3 L+ ^/ w2 {
3.3 V and 1.8 V (external)
; j% G8 Q: w0 N' D$ _5 ^ | 1.2 to 1.35 V (internal), + I# t4 V5 }3 k$ F2 ~$ V G
3.3 V and 1.8 V (external)# V) q7 T; v2 |( t' q; Y5 U# M0 z. p5 S
|
Maximum operating frequency- S3 m( m) M% A2 K
| 336 MHz: q5 K& M ~; j% k- @: ~
| 400 MHz
0 f, W2 g# x: f4 K4 t2 { |
Processing performance2 j& x7 a1 |$ a0 B
| 600MIPS, 2.3GFLOPS" _) k9 U& ^ M3 C5 i, ^. r
| 720MIPS, 2.8GFLOPS
" r `1 |, A* t4 h% o: Y, i' n% k |
CPU core. ~* v3 a& h" {- ?! y9 J
| SH-4A core
/ Q0 U+ |6 j6 _8 S |
On-chip RAM
9 u, B$ d: n4 j& K | ILRAM: 16 Kbytes% N7 O5 e! ?# b5 V
|
Cache memory& d' {5 {* U. ]' }; R
| 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data2 {) d% c I6 Q
|
External memory9 y$ }$ X( o4 s5 D
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus: N- z4 S( }9 B( @; \
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus, ~" j9 |: J$ c+ U& ^+ Y
|
SRAM or ROM directly connected to extension bus
3 J* y3 k" A' ^' l8 ?) o0 _( X |
Extension bus
, Z0 ?0 [: B- H4 Z/ M | Address space: 64 Mbytes × 35 d1 I4 ?: K" l7 x
|
Main on-chip peripheral functions
- d: m' c6 f, o | Renesas Graphics processor(2D/3D)
: K% Z/ E8 O v( K/ p( d0 b |
Display control: outputs for two screens (digital RGB and LVDS)7 {% a8 J: P" L! W% \9 ^: f
|
Video input interface
+ B5 ^6 m4 G0 L- I! G( v+ X |
SD card host interface × 2 channels* W" ]3 v4 C% w9 ]5 x# x
|
USB 2.0 host/function interface( c4 U8 w; D5 `% d! e3 z W
|
FM multiplex decoder9 M) p; w/ d8 h. c% R5 u+ W! ~
|
Controller area network (RCAN) interface × 2 channels3 p: I& q6 Q' Z( S
|
MOST interface module
1 w$ l5 k) R S0 b6 o% ~; F; q7 ~ |
Various audio interfaces × 4 channels
$ x9 i5 N( D5 `+ q7 N |
Dedicated DMAC × 26 channels' f( I3 r, v5 m2 W4 ~- q/ w
|
I2C bus interface × 2 channels4 v3 P0 X; T7 X* [
|
Serial communication interface (SCIF) × 8 channels
, z/ \' b+ W4 p( | |
Remote control interface × 1 channel
) d! _" p# c9 u3 `- U1 ~/ u% T1 Y% w |
A/D converter (10-bit) × 4 channels
% B+ z1 j* Z% e0 x$ @' z |
Timer × 9 channels3 Z" u1 d( u8 R+ {6 f
|
On-chip debugging function' s" B! f' W. o6 n3 m
|
Interrupt controller (INTC)0 R1 F0 c1 i! s, H: x$ m, j3 C
|
Clock pulse generator (CPG): built-in PLL frequency multiplier! Y* Y* U% F! l) J: b+ g
|
Power-down modes
9 E( |) w3 L& F8 P" @4 @ | Sleep mode
3 I0 j" J& K+ x9 g. ^. W |
Module standby mode: F, E/ k3 s. U" u/ T9 E) I
|
DDR-SDRAM power supply backup mode# v. s4 @4 s" K1 e; U
|
Package; Y- s) d9 p+ S
| 449-pin BGA (21 mm × 21 mm)
$ o# y! B3 o' c3 N6 O: G2 P) r |