Item7 I; H$ k5 n; T
| SH77722 (SH-NaviJ2) Specifications1 N6 W2 P2 h1 a) P% N' p& h
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Type name
( z4 X) E' u$ q8 E | R8A77722DA01BGV/ |' w1 ~$ V3 C8 T- L; c# l# _4 O2 {& ]
| R8A77722DA02BGV& h1 c9 u6 w5 M6 N) L0 T
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Power supply voltage
( h1 A& ~ a+ U% U* v" T | 1.15 to 1.3 V (internal),
- W# X7 l3 O+ r3 L8 \; W4 s! g3.3 V and 1.8 V (external)
' [- A. N# R: |$ V% s* u* [ | 1.2 to 1.35 V (internal),
& P0 s2 C$ b/ ?4 g" U" m- S3.3 V and 1.8 V (external)" L, Y- _9 d2 P9 X( q) t- T
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Maximum operating frequency7 z. E- c* U. T, h
| 336 MHz
. h; b; u2 e7 ~5 [ | 400 MHz, v8 S: A! j+ H8 w1 J& e, }
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Processing performance
3 R% R- }* s. L/ C4 N' V/ b0 ?# E | 600MIPS, 2.3GFLOPS* `* x1 w7 I7 V& G
| 720MIPS, 2.8GFLOPS
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CPU core) |4 y3 p4 I- W2 ?, g
| SH-4A core
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On-chip RAM
" \( a. h7 C+ @2 F | ILRAM: 16 Kbytes, j- a' b- i _; c; o+ |5 u8 _5 |
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Cache memory
6 t. f7 X' Q/ I$ X) b | 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory0 }- ~' s& m* m5 P9 i9 h& z
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus8 t3 Z d( i0 i% j
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus
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SRAM or ROM directly connected to extension bus, ?, S: h$ i+ s* ?: f
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Extension bus
# s0 A9 H' f3 k! l | Address space: 64 Mbytes × 3- Z6 F0 X# S7 E& N- @3 S/ n
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Main on-chip peripheral functions
+ v1 v, K; n4 q& f4 q4 s9 U | Renesas Graphics processor(2D/3D)
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Display control: outputs for two screens (digital RGB and LVDS)
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Video input interface4 G4 N' R; s5 ^
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SD card host interface × 2 channels2 {1 X1 m% M. @' h/ m
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USB 2.0 host/function interface( N* f1 g- ~; l4 j- s
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FM multiplex decoder/ B: T7 P- [9 M
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Controller area network (RCAN) interface × 2 channels
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MOST interface module
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Various audio interfaces × 4 channels& ?# P1 N& ]2 H2 n
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Dedicated DMAC × 26 channels* q' ^ K4 T0 q- F
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I2C bus interface × 2 channels
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Serial communication interface (SCIF) × 8 channels
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Remote control interface × 1 channel
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A/D converter (10-bit) × 4 channels
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Timer × 9 channels
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On-chip debugging function" J% {7 c6 s# ^
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Interrupt controller (INTC)- G+ z9 n" ~5 X; y# }! h
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Clock pulse generator (CPG): built-in PLL frequency multiplier
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Power-down modes
: j9 M, F- q1 }8 t& \$ |3 W P | Sleep mode
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Module standby mode
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DDR-SDRAM power supply backup mode% V( P4 w* r g
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Package7 j. L8 A/ B+ E% F7 I- \
| 449-pin BGA (21 mm × 21 mm), m( N! g3 g( \* G
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