Item
w1 b5 l+ e1 ? | SH77722 (SH-NaviJ2) Specifications
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Type name
; p$ @6 `4 M6 R0 \9 p7 U | R8A77722DA01BGV
5 Z6 n% T) r, D d9 ~1 Q | R8A77722DA02BGV
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Power supply voltage! x5 {6 x1 q6 \, V
| 1.15 to 1.3 V (internal),
. P$ K ?! w4 P. p* R' e1 k3.3 V and 1.8 V (external)" H6 T# Y. [% S+ }: h
| 1.2 to 1.35 V (internal),
( l- I( L3 Z" O( I. n; k& A3.3 V and 1.8 V (external)
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Maximum operating frequency* T5 @9 ?! }5 j$ `% y$ P3 b
| 336 MHz1 ], z) G. h/ \0 q& w& j
| 400 MHz
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Processing performance
b) [5 O- s3 w2 f2 J6 B | 600MIPS, 2.3GFLOPS0 G& R7 ]1 Q) b* t9 ^ p
| 720MIPS, 2.8GFLOPS( `" `6 P4 M5 o
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CPU core! Y+ H3 h0 z: N0 l
| SH-4A core# y3 I4 U5 n, y1 z9 r c
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On-chip RAM( c1 K" o7 X* @0 o. I( ^2 [% T5 ?
| ILRAM: 16 Kbytes
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Cache memory3 I7 z. f* g" S
| 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
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External memory
7 r% D2 x1 y2 N | DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus0 h& t, O6 O5 _" C1 j& D6 J+ w7 ^
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus2 a( W" Q _6 n4 ?) R
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SRAM or ROM directly connected to extension bus
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Extension bus- @' L0 }+ Q' q3 h t0 q( z |
| Address space: 64 Mbytes × 3
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Main on-chip peripheral functions
2 I- A5 y7 p& |" @ M' ^ | Renesas Graphics processor(2D/3D)
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Display control: outputs for two screens (digital RGB and LVDS)
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Video input interface- j% W$ Z) f/ E2 W
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SD card host interface × 2 channels
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USB 2.0 host/function interface6 L- H# {* _2 z0 h! o
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FM multiplex decoder0 i3 t/ O& U* H7 Q7 O! W' j
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Controller area network (RCAN) interface × 2 channels
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MOST interface module
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Various audio interfaces × 4 channels7 f8 m! z1 z1 w1 o8 }
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Dedicated DMAC × 26 channels
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I2C bus interface × 2 channels+ U* S; \3 c4 Y* Q& Y# m* u
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Serial communication interface (SCIF) × 8 channels
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Remote control interface × 1 channel
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A/D converter (10-bit) × 4 channels3 A7 p) U) J' z* Z) i5 e, @3 [: m& j
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Timer × 9 channels
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On-chip debugging function% l5 E7 [9 m7 X$ C
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Interrupt controller (INTC) f* P$ [" _5 j% T# a U3 |. @
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Clock pulse generator (CPG): built-in PLL frequency multiplier* ~9 }% N6 ]4 t4 d) t% Q
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Power-down modes
" B1 w$ F1 N# y9 u3 u' v4 h& T | Sleep mode$ ?+ D0 x( C! F- H( ^4 e
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Module standby mode% x) \8 N, J/ n# A5 V
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DDR-SDRAM power supply backup mode
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Package$ {5 n! G" h. l3 G( E7 d7 u
| 449-pin BGA (21 mm × 21 mm)# {$ |2 T' ?3 ?1 y a
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