Chip123 科技應用創新平台

 找回密碼
 申請會員

QQ登錄

只需一步,快速開始

Login

用FB帳號登入

搜索
1 2 3 4
查看: 34707|回復: 13
打印 上一主題 下一主題

[問題求助] 對本版討論有興趣者請進來報到!點名囉!

  [複製鏈接]
跳轉到指定樓層
1#
發表於 2007-4-29 21:32:51 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
這個版是熱門領域---EDA 達人愛好者的!你逛這一版,是因為你專業從事EDA 相關技術應用?還是只是業餘愛好EDA 者?:o 0 y9 Q8 o# ?" m3 f. _. N
這版需要您熱情參與討論,與大家分享你的問題,你的經驗,你的工程師專業,你的技術鬱悶,你的技術欣喜!
( V# ]2 N* w5 z( X# f
: {8 _( p( y$ N% r+ Y# X正面:abc1973:好網站是要靠大家維持的,這樣才會發揮Web2.0的真正功能,就是大家一起成長啦^^ . G. Q- G5 _& X. |; w
反面:andy2000a:台灣的討論 好像比較難分享 如同一堆 rd   自認為自己know how  跟本不願和人分享
) a; S5 g* e! g- m: m, L& }+ W
: l8 ?9 _6 i1 @$ Y$ s2 P: x$ j
1.討論主題:
% T9 m0 p2 x! ~4 i/ P/ M7 n% _+ s* l; L/ C! J0 i2 S) ?" M/ v
   你難道都沒有這些需求麼?不需自助助人麼? 問題求助 好康相報 經驗交流 精華出售...% f5 u3 y5 C2 N9 d
   這些技術領域還不夠寬廣?都不需要討論麼?  民意調查 經驗交流 議題探討 市場探討 ...
8 H8 B5 F, a: S
1 i( Y: Y' Y; b, t' T: m' t+ a: N
2.副版主人選:
, B* v& y7 T8 l, R3 ~# ]. C6 Q
) I% w5 P/ G* f$ r! e6 [   本版先前頗有人氣!但可能因為尚未有正、副版主人選,以致未能持續討論風氣?哪幾位願意來身先士卒,組織社群,造福蒼生?: f  F  Z  J& {6 Y: ^
   誠懇呼喚以下高手如雲的大大(大俠):! c% g) O2 ?  _

0 v! W: r1 D* d; g( B: D   roger2003, henrylai, hgby2209, lcctsai, klim, nemo, leogao99, ty0001, hsd123, imems, edward0519, treebug, binjon, jordanplus, waynez, henrylai, 西湖水, ty0001, brian_shu, yeali, jlian168, staric, ryanchen, jimy, tengomark, chihsinchang (阿猛), scping, chjan, hycmos, waynez, hgby2209, kingfiretai, xiexie57, duckdh, ceusiin, dellmikkon, pheychang, taylor_su, richc, Y先生, jordanplus, brian_shu, huhu, star123, scounix, stella321, scounix, staric, d8731502, haha, treebug..." S4 K. ]+ ^! T: v" R4 n' r* m1 v

% I  Q5 z8 Z9 L& I' P+ G" ~& emasonchung:討論區會有多少人參與要看大家能否在這裡得到收穫吧 夠專門領域的論壇會有更多專門領域的同好及專家前輩參與討論 板主的話應該有熱情再加上專業領域的人才都可以勝任阿
2 H0 K, n7 a# |$ ~: g- J% {9 [" L$ T
3.激勵方案:
2 ]3 {& C" F' j, G9 v8 Z% \0 h7 Z8 D- t
  如果你也有意加入團隊:12 位正副版大聯合發佈令 ( ~! Z& H' ]: N; D
                                   chip123知識社群核心管理團隊組織運作草案  
+ n% \& z+ Y2 e- @! N" t* D                                   技術討論版各招募5位副版主,有意者請於各版以應徵版副發帖
( p2 f* L+ Q/ \) ^3 ~, m8 `/ N/ x
  讓大家群策群力共同  為台灣論壇發聲...以技術定高下,以專業論輩份,以經驗帶成長,以感謝為鼓勵...
, k4 ]& f2 j# u1 a# @( |2 p# T. ]9 L# X) x5 y) Y' J* s2 {
  如果您希望這個版有所發展!並對你職場上有所幫助!請不吝進來報到!表示意見!熱情參與才會學得更多!
分享到:  QQ好友和群QQ好友和群 QQ空間QQ空間 騰訊微博騰訊微博 騰訊朋友騰訊朋友
收藏收藏 分享分享 頂5 踩 分享分享
2#
發表於 2007-11-28 09:18:06 | 只看該作者

EDA 版建議的 Presentation 討論主題

有這麼多可以討論的... 昔日出現的大家卻不見了... 是都到別處看人家討論麼? ( [; [7 v% N4 e+ `

4 P* W9 o$ T/ f想把你的設計經驗和大家分享嗎 ? 想告訴我們你如何突破設計挑戰嗎 ? 舞台是您的 ! :o
8 D! U1 A, Y! R% x5 |! Vhttp://www.cadence.com.tw/cdnlive_2007/main_02.htm3 R% B; |& z+ `$ b
0 T  s! S) e0 }7 y6 ?2 u
Functional verification
Power-aware functional verification & modeling
Transaction-based verification, modeling & acceleration
Hardware/software co-verification - ISX
Verification planning and management
Testbench development and automation
Assertion-based Verification
Formal Analysis
Simulation debug and analysis
Analog-mixed signal system verification
Silicon debug in-circuit emulation
Platform VIP Reuse
Digital IC design
RTL synthesis
Formal verification
Low-power design/estimation in front end
Low power design implementation and analysis
Design for test/yield/manufacturing (DFT, DFY & DFM)
Constraints management and timing analysis
Hierarchical layout, prototyping, and planning
Physical optimization, routing and timing closure
Dealing with ECOs
Coping with variation during implementation
Signoff (timing, power and SI)
Physical verification (DRC, LVS, EM)
New technologies challenges
IP design and reuse
High-performance design
Custom IC design
Analog/RF parasitic extraction and simulation
High-frequency challenges and solutions
Statistical simulation
Circuit optimization
Full custom floorplanning
Physical automation/ optimization
Physical verification
Voltage drop/electromigration
Mixed-model/mixed-signal simulation and analysis
Test for analog/mixed-signal designs
IC 6.x Adoption
Deep submicron challenges/solutions
Modeling/characterization
Analog/Mixed signal methodology enhancement
RF Design methodology enhancement
Silicon-Package-Board
Front-end design capture
Constraint-driven design
Design partioning and reuse
Library and data management
Integration with PLM systems
Infrastructure and customization
Interactive and automatic routing
Design for manufacturing and testability
Signal and power integrity analysis
Simulation model development
Multi-gigahertz design
Design process and automation
Algorithmic-based model development
Designing in DDR2 memories
Silicon/Package co-design
Rapid feasibility prototyping methodologies
DFM verification of complex IC Packages/SiPs
Package-On-Package design techniques and challenges
RF SiP methodology enhancement
Special Interest
OpenAccess
Reliability modeling
Design for test/manufacturing and RET signal integrity
Design reuse strategies
Impact of standards on design optimization
Configuration management
Process design kit automation
Platform-dependent methodology flows
Linking of design and fab data to improve ramp yield
DFY/DFM optimization techniques and results
Interoperability
3#
 樓主| 發表於 2008-2-18 12:37:08 | 只看該作者

Where are you going to, EDA designers?

以下是Mentor Graphics upcoming IC-Focus U2U 使用者大會 希望能透過客戶彼此面對面的經驗分享,增加設計技巧,以期將產品的效能發揮到最高效益。0 l$ y; _; k" N9 N9 u
3 L5 [3 U3 Q: q
Call for Papers!
, D" c9 p" @2 }! w& w; \5 Y5 o0 A/ G
+ a0 X5 D$ ?  N) J' {0 G想和大家分享您的設計經驗及解決方案嗎!$ A$ X. L( o& ?& f2 C
您就是我們相中的專家!就是您!千萬別懷疑!
9 j  _% x; s  |1 @* N+ H, i+ u

+ Q/ `1 F1 ^# I" d分享您創新的設計解決方案和成功挑戰困難的案例。
1 X+ I& f; o# L0 [5 s$ E從下列主題中挑選出您欲分享的 Topics 及Abstract:5 @) V) r8 X4 }, W3 {
, o6 ~% y1 I7 u# ]9 A/ s
Incremental DRCResolution Enhancement Technology (OPC, Scattering Bar)
Parasitic Extraction SolutionFormal Verification & Clock Domain Crossing
Design for ManufacturingAdvanced Verification Methodology
Analog/RF Fast SPICE SimulationLogical Simulation
Memory BIST, Boundary Scan, Scan Insertion, ATPG, Test Compression, Scan Diagnosis
您需要登錄後才可以回帖 登錄 | 申請會員

本版積分規則

首頁|手機版|Chip123 科技應用創新平台 |新契機國際商機整合股份有限公司

GMT+8, 2024-12-29 09:04 AM , Processed in 0.179010 second(s), 17 queries .

Powered by Discuz! X3.2

© 2001-2013 Comsenz Inc.

快速回復 返回頂部 返回列表