STD Cell Data Prepare 中 wire track 的問題?

hgby2209

Standard Cell 的 Data Prepare 的過程我會去做 axgDefineWireTracks
然後再做 axgCheckWireTrack 來 check wire track, 但是做完 axgCheckWireTrack  
7 c+ |* i4 E% u5 e9 F$ X之後卻有如下之 Meaasge:
2 L# r( u: s7 T( m  s/ w$ z) ^3 U
+ H8 V' F* [/ Y: q: A******** Pin Access Analysis *******
8 _- V( I, y: ?0 _  Q  K) U/ g1 X** # Cell Masters    =  1000
* Z) h( X4 E6 S** # Ports (logical) = 2500
; h4 _' T' L& K( F2 H# G** # Pins (physical) = 2500
** # Pins with no good access point on Grid (V&H) =   5 ( 0%)
) N7 N: N7 h5 p  c# u( }; k* t** # Pins with no good access point on Ver-Grid =    5 ( 0%)

請問下面這兩句是代表什麼意思呢?
** # Pins with no good access point on Grid (V&H) =   5 ( 0%)
** # Pins with no good access point on Ver-Grid =    5 ( 0%)
3 f" S% X% l) s3 L: Z0 M3 {
. x$ j" S+ k# P) d' [* l若是代表有錯誤的話是否要 Fix 呢?