請教如何以兩個clock寫入同一個暫存器?

shlee

假如有兩個Clock, CLKA, CLKB, 當CLKA Raising時, 暫存器A要寫入0, CLKB Raising時, 暫存器A要寫入1, 請問如何以Verilog/VHDL implement??重點是要能Synthesis成一般電路, 謝謝回答..

' d9 v1 F& O  I$ ][ 本帖最後由 shlee 於 2006-10-31 01:32 PM 編輯 ]

ssejack1

CLKA rise/ CLKB rise, 如於 asynchronous system 中 使用 gate delay 取的 rise edge 的 pulse,
( ?& z4 d5 Z% t6 m8 v PLUSA = CLKA & (!CLKA_DELAY),PLUSB = CLKB & (!CLKB_DELAY);接下來以 RS 正反器就可以啦!
2 {% |* d' L, |5 G, B  Q/ w( [
if ( PLUSA = '1') then
   OUTPUT <= '0';
elsif( PLUSB ='1') then
' L# G9 p3 E8 U5 q: s  OUTPUT <='1';
5 m8 S1 L0 d- S9 w8 |1 eend if;

fpgacpld

Actually, you must check the library, for example, when using Xilinx FPGA.
" D: l2 d& N" k+ p0 ZThey provide Dual Edge FlipFlop, You can just instantiate it.
% B+ c6 T% c9 w( l) O8 _7 F
IF you're using ASIC or Other FPGA product, usually they also provide similar component!

* L$ s& {- z. ~* D; A8 jthe attached example fdd.jeg is the Xilinx Dual Edge FF component!

tommywgt

如標題所示, 這是一般的做法, 使用FPGA時就如同fpgacpld所講的呼叫library, 用ASIC的話也是有相對應的library可以用