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AMD Geode LX 800@0.9W處理器
General Features
8 T* e" i- e; Z% O0 O) }/ }1 R3 c' H: ^■ Functional blocks include:
* u1 a6 h( M5 _! s; x5 ?! K— CPU Core0 g: @ e, M' l; M" v$ P2 M0 S
— GeodeLink™ Control Processor3 h+ F5 m! |4 ]& H8 n6 y
— GeodeLink Interface Units) m u+ N7 X) Y- d* [9 K, o2 `
— GeodeLink Memory Controller9 h0 r5 t" \2 o( \' P3 u4 k- W5 u2 u
— Graphics Processor
' k$ [" H/ m9 a9 |. p" T! s h: R— Display Controller" \& O/ M3 p5 ~/ ]2 x
— Video Processor
# [4 }; Q9 I0 n% `3 ]– TFT Controller/Video Output Port# ?7 Y3 i! m" i2 e9 E
— Video Input Port' a1 q$ E8 K6 x4 j8 ~
— GeodeLink PCI Bridge8 n. s* U( U! C- p& O6 W
— Security Block: L8 U6 p) b9 Q( p! d# ]* F. q/ F6 u
■ 0.13 micron process) w5 u g3 j4 f# @9 P
■ Packaging:
7 Z% F2 x" X, _4 ]— 481-Terminal BGU (Ball Grid Array Cavity Up) with
" Y( v, s# i! [/ C5 [7 f4 C# Q! Linternal heatspreader8 [9 Z; h: s' w! Y0 v
■ Single packaging option supports all features
& ~# ?1 d5 p3 N' nCPU Processor Features
& `: F$ v$ Y, E, B■ x86/x87-compatible CPU core
0 X5 c2 f- @2 O9 A7 A: `■ Performance:
* o; F' B" d; N: X— Processor frequency: up to 500 MHz
3 X0 e. k" {; O+ p) {— Dhrystone 2.1 MIPs: 150 to 450; T' I3 E5 p: B
— Fully pipelined FPU
- |) n& m [* y- M8 J6 m■ Split I/D cache/TLB (Translation Look-aside Buffer):$ n" s& t7 k# T9 E3 `: d+ c i
— 64 KB I-cache/64 KB D-cache
; B, A! B" X0 r. v— 128 KB L2 cache configurable as I-cache, D-cache,
8 ^5 d5 `( e# _+ H4 _or both7 A4 y3 w, U" x& g! z- B
■ Efficient prefetch and branch prediction
5 d& ^) H4 P3 d, H: y■ Integrated FPU that supports the MMX® and1 H2 h4 `6 K/ t# Q
AMD 3DNow!™ instruction sets/ X z* B1 Y' y# k- a/ h
■ Fully pipelined single precision FPU hardware with
y0 Y' K' Q% Z" e) s: p9 Mmicrocode support for higher precisions2 t/ T% H+ @& t5 A
GeodeLink™ Control Processor
- A" l8 X4 Y; q4 R: ~; |& Q■ JTAG interface:
: x7 f/ z6 j$ v* p— ATPG, Full Scan, BIST on all arrays
& |. U- p' ]- C; c' h6 ?4 o— 1149.1 Boundary Scan compliant6 D+ t* p6 S- W, P
■ ICE (in-circuit emulator) interface
2 U- S4 |& `, z+ \■ Reset and clock control
" `$ o$ C( Q6 h7 K■ Designed for improved software debug methods and
4 ~! L7 N0 q3 j. M8 ]; k0 Tperformance analysis/ |7 m' b3 t' f& p3 w
■ Power Management:* K) ?/ c- R- U$ L! l5 P, j
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @+ v4 Z: k P2 B
500 MHz max power& s6 w: x0 U# C4 H
— GeodeLink active hardware power management+ B4 x' z, o# Y7 l4 H: A2 F
— Hardware support for standard ACPI software power
* [1 B5 t9 I* c& O" xmanagement) g! L& G% Y! o# c9 `$ L
— I/O companion SUSP/SUSPA power controls- _9 b x( J( t( I8 m! v0 q
— Lower power I/O+ ~$ H7 n- N0 a" K* l% e% ?
— Wakeup on SMI/INTR) X0 ]. U! t2 u* V/ \* C6 ~; n( _; H
■ Designed to work in conjunction with the8 a- a) w/ p2 u" e5 j6 v! L7 ~; P# f
AMD Geode™ CS5536 companion device9 p' `3 S8 C" Y
GeodeLink™ Architecture v4 V. V8 m4 ?( b
■ High bandwidth packetized uni-directional bus for+ j0 S5 p, u& X
internal peripherals* m0 t: e/ \! a
■ Standardized protocol to allow variants of products to be! i0 v: [& c1 s- P
developed by adding or removing modules
% H9 [% v4 p: ]; A! p■ GeodeLink Control Processor (GLCP) for diagnostics |) ]7 R$ g, ]+ Y8 h$ p6 g
and scan control+ S1 L% H, N5 a" a" c
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
# E2 {6 o: H2 V( T% v$ ?# dGeodeLink™ Memory Controller, Z- q% T0 ?2 h. J
■ Integrated memory controller for low latency to CPU and; n w9 o6 b5 v( i) \
on-chip peripherals X" |. E; c6 v4 x( H) I
■ 64-bit wide DDR SDRAM bus operating frequency:4 R; P# q8 y6 K$ H% l
— 200 MHz, 400 MT/S* J7 d3 W) }; Y0 |: }
■ Supports unbuffered DDR DIMMS using up to 1 GB
+ e- ?/ u( u$ v. oDRAM technology
# x. f6 h4 m# ?* v2 ^% Y+ w■ Supports up to 2 DIMMS (16 devices max)
8 M4 m, o, c J, k2D Graphics Processor+ W) C0 J d% S4 H7 c" m
■ High performance 2D graphics controller8 `, p8 e( g0 L5 j% x
■ Alpha BLT8 s; S7 y5 R7 y: ^, |& d; A
■ Microsoft® Windows® GDI GUI acceleration:; @, `" C7 A2 G" b3 T6 ]
— Hardware support for all Microsoft RDP codes* D/ Z# D' O) `) B; O A) c9 o
■ Command buffer interface for asynchronous BLTs8 _+ z5 i3 C- ?2 T! Q, F
■ Second pattern channel support, `0 P/ b/ N/ E" k
■ Hardware screen rotation |
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