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AMD Geode LX 800@0.9W處理器
General Features* W# A8 S9 X/ w8 F, V& L
■ Functional blocks include:3 x8 p1 i/ e" g0 | Y
— CPU Core
* n* D% w X% v* `7 Z— GeodeLink™ Control Processor
0 z' k" f9 g& w* `, r! w— GeodeLink Interface Units9 w. z' f2 z9 Z2 E2 ]
— GeodeLink Memory Controller$ e1 O6 ~1 r; v4 e) Z% ^% m3 |
— Graphics Processor
0 v5 j, I3 ]6 W# Q; m# O6 `— Display Controller* a; d% U, ?, d7 v( m
— Video Processor
- p% p- n* P2 E: i6 a# r/ \– TFT Controller/Video Output Port
! i% f4 r! d5 W" T% S/ K. ~— Video Input Port+ I7 |6 o$ ]5 N: A9 {* N
— GeodeLink PCI Bridge
# z- L+ z0 ]# R1 h0 A/ K) D— Security Block
6 h7 t2 x& `4 n0 T- r■ 0.13 micron process. A1 u9 O& Z N" C* D
■ Packaging:
* w8 R+ T' l+ j* X& P— 481-Terminal BGU (Ball Grid Array Cavity Up) with
3 |* _* y6 T! |1 A5 `& }4 Hinternal heatspreader
" z( H) j9 q: K$ T8 E) A) `■ Single packaging option supports all features
/ a% i( z3 H e. ?, N$ oCPU Processor Features; |+ b! B: X7 ?! g' M6 o3 {+ X
■ x86/x87-compatible CPU core
8 L0 u* i5 l6 y5 |: i6 |/ H; _' r■ Performance:/ l! U6 o- D3 Z2 P* k2 S! `' P4 T
— Processor frequency: up to 500 MHz
( v" \8 c/ ?" m( j— Dhrystone 2.1 MIPs: 150 to 450
+ `2 S' N' `: g& M+ {— Fully pipelined FPU
8 \* n R) b- b8 r( |* M■ Split I/D cache/TLB (Translation Look-aside Buffer):5 x O! Z( t5 R
— 64 KB I-cache/64 KB D-cache+ ~4 R" P( }7 Q, s" G1 F5 S6 `- I
— 128 KB L2 cache configurable as I-cache, D-cache,
+ m1 D' c% Q/ U' K2 P* b% Cor both) U+ d/ _) B o. n/ i) i$ L
■ Efficient prefetch and branch prediction
2 ?7 r3 s* v* p& j8 |$ t D; J■ Integrated FPU that supports the MMX® and7 m1 l. V1 B" a& l
AMD 3DNow!™ instruction sets+ E' M$ P# C' r2 ~8 ]- ]5 E
■ Fully pipelined single precision FPU hardware with
- u" M6 ^# ?6 [. h# C7 vmicrocode support for higher precisions4 \4 M1 ]2 V0 e0 ~; Q5 I( ]
GeodeLink™ Control Processor/ D T- z/ R$ d/ q" _& b
■ JTAG interface:
2 r l% d7 p# l! @( f— ATPG, Full Scan, BIST on all arrays
, U' H( H2 t4 m" e9 Z0 j$ C% Z! R— 1149.1 Boundary Scan compliant
+ W2 ?9 w- A K■ ICE (in-circuit emulator) interface1 z9 |! v/ C2 T$ n# ], o- E
■ Reset and clock control
" Z; i- ~; ^8 @! ?■ Designed for improved software debug methods and( @8 ^ _# P `. M8 O% F/ O0 [
performance analysis. x4 g1 W3 @4 N( n: K
■ Power Management:4 E2 t+ p3 z: D
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
# o7 d! S C d" o) b500 MHz max power
/ c# d! C% o" `3 r— GeodeLink active hardware power management. h! ~( z- V7 Z
— Hardware support for standard ACPI software power9 Y, I$ S. }5 X
management
, g* ^5 w. {; T" k& B— I/O companion SUSP/SUSPA power controls
5 z" S9 Z+ I2 e4 H/ }& U— Lower power I/O6 s4 b. I2 E% m7 Q6 H* R6 g
— Wakeup on SMI/INTR
7 p5 H! c# o9 n6 P■ Designed to work in conjunction with the3 t; N9 I4 t1 s) N
AMD Geode™ CS5536 companion device+ ` F' L, E4 Z( _- e* t& B
GeodeLink™ Architecture8 E) G0 E' q! |
■ High bandwidth packetized uni-directional bus for7 X3 o* I2 l* T X0 x
internal peripherals9 T" M6 Y; Z% V, R( o; s5 `. {
■ Standardized protocol to allow variants of products to be
/ ?$ Z6 l( Z+ E; U6 v8 r+ Adeveloped by adding or removing modules
% ]* B0 Y: E1 G; G9 c8 H■ GeodeLink Control Processor (GLCP) for diagnostics
' V9 d6 O9 P' x5 N1 kand scan control
; d- C" g5 V9 U4 H0 P■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
4 s- _+ i8 \8 G: f* MGeodeLink™ Memory Controller
6 F. k# H }5 D! a$ T■ Integrated memory controller for low latency to CPU and% K! s# ]9 s0 Q y# A2 `6 j
on-chip peripherals1 a4 @6 {5 k) i2 J6 D
■ 64-bit wide DDR SDRAM bus operating frequency:
- X7 |& Y7 O1 U# c/ P) U3 J0 b— 200 MHz, 400 MT/S$ n8 f' o6 ?2 l' Z
■ Supports unbuffered DDR DIMMS using up to 1 GB
7 c8 R+ v6 p6 `! a6 ^( r- ]DRAM technology4 L/ y& j& S, F/ f; J
■ Supports up to 2 DIMMS (16 devices max)& U4 m& y, U+ l3 O# f) W8 l
2D Graphics Processor
7 L0 n2 f: p0 O8 M/ G; V■ High performance 2D graphics controller
0 a( @4 P: E( b, e8 l$ E7 z6 A" Z% A A■ Alpha BLT" O/ f2 y% q: b' D* ?
■ Microsoft® Windows® GDI GUI acceleration:7 E E$ l+ y1 ?. p
— Hardware support for all Microsoft RDP codes
- m( [, d6 L5 A, h$ H, E3 _■ Command buffer interface for asynchronous BLTs
W8 x3 F- G3 p■ Second pattern channel support# r% ]3 H3 O8 G8 L. g5 g
■ Hardware screen rotation |
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