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AMD Geode LX 800@0.9W處理器
General Features- j1 W5 t, a( P3 x- U, g( X9 [
■ Functional blocks include:$ ^& |( e. A6 l. ^0 g( z: F( [* a
— CPU Core" p+ z ?' t7 N
— GeodeLink™ Control Processor: y' T5 v8 L5 C& |2 s
— GeodeLink Interface Units
& D5 W, M, N" _# r7 a* z6 l— GeodeLink Memory Controller M2 @9 p; i4 }1 S+ l$ ?. ?
— Graphics Processor) O% H3 }; ~8 M7 i
— Display Controller: Y! _0 f$ T8 k5 n( X
— Video Processor% Z& j, R5 G( C6 @2 S
– TFT Controller/Video Output Port
& f9 Q# C m% X% {0 i3 c. c— Video Input Port: y7 e( u+ T# j5 @+ |
— GeodeLink PCI Bridge) Z# K" |; \ i6 k3 T
— Security Block$ ~& _. I( [' G% l
■ 0.13 micron process S5 Z9 s# ~$ C S% v" W% s, Z) J! v) M
■ Packaging:
) o4 {6 L- x m— 481-Terminal BGU (Ball Grid Array Cavity Up) with2 {& N7 |( @- l; c0 `
internal heatspreader. p* t! P* q+ `8 k) h `6 t' M/ S
■ Single packaging option supports all features9 Y' q9 g- f7 _9 a8 ~& v O5 a% A
CPU Processor Features
# F" [2 T8 v' K v+ \■ x86/x87-compatible CPU core
; [' c# }! |& B7 {) b T7 z■ Performance:6 Z+ Y, l& o J4 K
— Processor frequency: up to 500 MHz
5 r: u1 _' H& k, A& m— Dhrystone 2.1 MIPs: 150 to 450
/ K; p) d+ e" R: k$ d! P— Fully pipelined FPU
9 N6 R; A, k& }3 k1 l■ Split I/D cache/TLB (Translation Look-aside Buffer):
& a* h) S: u' l6 W+ L3 J2 k— 64 KB I-cache/64 KB D-cache
. ^+ U4 r4 s8 {9 N— 128 KB L2 cache configurable as I-cache, D-cache,3 w0 Y( m* f2 e' o; j0 g6 P2 k: u
or both
5 G, F+ f5 w! r, R. L+ I6 x■ Efficient prefetch and branch prediction
1 l# K- D- |& [1 m: l) r, H6 z& d■ Integrated FPU that supports the MMX® and2 j5 `$ V2 w5 c6 M% s
AMD 3DNow!™ instruction sets
- s" x. f G/ j, @/ O4 Z `■ Fully pipelined single precision FPU hardware with; B# P% ~" ~2 K5 M0 v
microcode support for higher precisions
3 n4 Y% R: M* y( `6 f* t, R IGeodeLink™ Control Processor- w/ h8 X7 ?# g$ H1 V! e
■ JTAG interface:$ u" @! }/ w7 }8 k% \+ V' @
— ATPG, Full Scan, BIST on all arrays5 W: V) p7 L4 _8 c4 b) s4 F
— 1149.1 Boundary Scan compliant
' N: @8 ^ v. l) w# s■ ICE (in-circuit emulator) interface
& S( | Z' I; e■ Reset and clock control! p: B: ^$ M# s9 e9 {6 g5 M
■ Designed for improved software debug methods and4 e J* C5 O4 a) m/ ]4 ~2 E; U9 R: v
performance analysis
: ?& _- I/ x% v4 ^- ~■ Power Management:3 O6 e, m5 e+ u3 U$ h. H/ C% s
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @8 J- y0 z6 D7 Q8 L" C
500 MHz max power, K) [& h4 a6 R Q' e& c1 X" J, H: O7 @
— GeodeLink active hardware power management0 J! m5 I- [2 U- ?9 |) l/ z {
— Hardware support for standard ACPI software power
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— I/O companion SUSP/SUSPA power controls
% T" `9 B( c3 [1 h! ~# `— Lower power I/O
3 J6 B& b- b" f4 L, g: z' Z3 D) F% L— Wakeup on SMI/INTR# J# W) z/ @* t; G& d% t
■ Designed to work in conjunction with the2 ?' p6 R' Z& E
AMD Geode™ CS5536 companion device
R* B3 H5 [5 K& v0 x1 k7 ZGeodeLink™ Architecture
, Q) o5 s0 Q9 e1 Z■ High bandwidth packetized uni-directional bus for
5 c, @% K1 P% y6 d9 w3 |internal peripherals% Z% _: e9 ~& A5 _; n, B
■ Standardized protocol to allow variants of products to be
& |4 ~, v$ B( u' l% N% o9 pdeveloped by adding or removing modules7 l" W- n& V9 S" D0 F
■ GeodeLink Control Processor (GLCP) for diagnostics2 X' J' j. G* X! E8 D/ b; f0 X( D4 F
and scan control
# d9 M4 {1 y/ @; c■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
+ p5 b+ h; a7 @GeodeLink™ Memory Controller
. G. ]4 R2 }( O; m/ w■ Integrated memory controller for low latency to CPU and
8 H' V$ S8 S3 D( u3 x4 Z3 X8 uon-chip peripherals
: g, c4 y" b z3 f2 G0 m$ ^% w( v■ 64-bit wide DDR SDRAM bus operating frequency:
' n& d( P; _% L" n' ]! a8 H3 a: n8 q— 200 MHz, 400 MT/S% t8 k' ]5 w5 Q, ^4 x1 f- X& n) L
■ Supports unbuffered DDR DIMMS using up to 1 GB8 B: S7 x7 b+ @! b9 a J9 a
DRAM technology+ I5 q8 j, A r8 w
■ Supports up to 2 DIMMS (16 devices max)
, o& C) i4 J* D- F+ S0 b6 A2D Graphics Processor! R. Z |& f- _) u% J1 [" O% o
■ High performance 2D graphics controller5 _1 R3 q; _* s- g
■ Alpha BLT
4 \6 T+ w, g3 B; T■ Microsoft® Windows® GDI GUI acceleration:6 c9 r. ]( Y# K
— Hardware support for all Microsoft RDP codes7 o! V+ r" a2 t
■ Command buffer interface for asynchronous BLTs% d" N1 x6 l% s; E" X( e
■ Second pattern channel support
; ^' ^& \. _3 \- S- {0 i■ Hardware screen rotation |
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