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AMD Geode LX 800@0.9W處理器
General Features
# [" f, A& j# H1 |3 t■ Functional blocks include:
1 M2 R5 F& F- F, j6 A( J b— CPU Core
$ L# z* R5 p# @0 H— GeodeLink™ Control Processor
- x. K# W7 g6 }* j— GeodeLink Interface Units# [ i ?; H$ t7 A P+ K- H% w9 V
— GeodeLink Memory Controller- A2 ^9 R$ d9 A3 w: G
— Graphics Processor
* o4 ~$ s, I% E— Display Controller
& D/ [1 |; _6 f1 j% ^— Video Processor
8 Q0 v1 o' ]: p: e+ }1 Y4 @+ b% L– TFT Controller/Video Output Port0 K0 ]) D$ j$ j' p7 o' ^2 x
— Video Input Port
8 I2 P c. Q6 v& W— GeodeLink PCI Bridge+ B$ c( t/ w. L" y* ? y3 x# l$ b
— Security Block* p) C& P! x. @; |7 ^* W9 i
■ 0.13 micron process
8 S1 j% h% i5 E9 t■ Packaging:
! O3 `8 F' a( J8 R— 481-Terminal BGU (Ball Grid Array Cavity Up) with) N. x, F# U' M; {
internal heatspreader
( s. s" Y% y& L) q6 }■ Single packaging option supports all features
6 L) j" t* f7 f& d6 e& tCPU Processor Features$ H8 g- l4 ~& h2 r8 A2 Z
■ x86/x87-compatible CPU core
3 F) P# T7 e2 |! ~■ Performance:
% J0 ~% ]- x" Z2 Z7 E- N1 i% F5 N v! p— Processor frequency: up to 500 MHz
! G' q U- y+ n" j1 z— Dhrystone 2.1 MIPs: 150 to 450
2 ~- p B* T7 B3 B9 G! Y3 l( @( J# n- U— Fully pipelined FPU$ W) M) @6 j$ ^( [& R
■ Split I/D cache/TLB (Translation Look-aside Buffer):# U! B$ F. K$ j# a; s5 T
— 64 KB I-cache/64 KB D-cache$ I% o5 E; n9 c
— 128 KB L2 cache configurable as I-cache, D-cache,
) o( h# v8 l. s/ ]/ W7 Wor both
# x( }2 x" L/ \3 @6 @6 F* e■ Efficient prefetch and branch prediction
" U" Q# G; g2 q■ Integrated FPU that supports the MMX® and. @, S1 S7 _$ n( r
AMD 3DNow!™ instruction sets
7 J+ k* ], F, Y6 K■ Fully pipelined single precision FPU hardware with
" |' B* m* x' A$ [3 N$ P1 e+ Kmicrocode support for higher precisions2 r6 P* A0 g& l6 f3 f( g. [ e
GeodeLink™ Control Processor! k% e* A$ o0 @9 W, j$ G, ], V
■ JTAG interface:
4 b% K7 F+ t( G6 @8 w— ATPG, Full Scan, BIST on all arrays
9 y% F8 q' f* d+ Q# ~— 1149.1 Boundary Scan compliant
5 A4 V, \8 J( l■ ICE (in-circuit emulator) interface- B6 I& T+ z l+ V% {" K" d
■ Reset and clock control, b1 Y W' `( Z. E2 E o
■ Designed for improved software debug methods and
p. N* z( R( Wperformance analysis- i- ` |9 j4 ` e8 x
■ Power Management:3 o8 U; O k9 z# r3 A/ W. L. r( w# O
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
6 L1 c$ {" E/ n2 w' B! V500 MHz max power1 f4 J9 O- l) J7 I4 ~ Y
— GeodeLink active hardware power management X: G3 M4 V p
— Hardware support for standard ACPI software power. a: j2 g7 w: _1 X4 o
management
# E8 e2 [( L0 B; T+ I— I/O companion SUSP/SUSPA power controls
' r& ^" e6 X9 t8 a0 W+ }, ^— Lower power I/O
( a" b9 w, `, a$ @- X' l— Wakeup on SMI/INTR0 E; B2 e$ \' K" a, u* f$ a
■ Designed to work in conjunction with the1 ^8 d' Q. e+ J- w# G
AMD Geode™ CS5536 companion device
" n% p) S" `) w- O% \GeodeLink™ Architecture
% S; n! M1 ~6 C■ High bandwidth packetized uni-directional bus for( |3 f% ?7 A8 U: u
internal peripherals
1 d) U. Q ?) E+ k( j' K. e1 b■ Standardized protocol to allow variants of products to be
. u6 m6 z1 ^% a! ~6 B- P k Zdeveloped by adding or removing modules
* F9 Y+ b' T. i: E4 m7 _& y- L3 ?3 K■ GeodeLink Control Processor (GLCP) for diagnostics
# n+ ~5 Y% } Dand scan control" C3 t) [ y0 Z* Y
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect$ B1 m U. L3 @" O# V
GeodeLink™ Memory Controller2 R1 a$ H% v$ U
■ Integrated memory controller for low latency to CPU and. N* Y E4 _" S" ^
on-chip peripherals, M" Z5 i0 p# k6 C+ N. M- o
■ 64-bit wide DDR SDRAM bus operating frequency:
$ A5 z) p/ j3 k/ I0 [- F& M& V/ r6 X— 200 MHz, 400 MT/S/ f+ n5 V' t9 b$ P
■ Supports unbuffered DDR DIMMS using up to 1 GB
4 ~( T+ ]4 |. Q$ |; ?: ~3 UDRAM technology7 B- A- ?% c, n
■ Supports up to 2 DIMMS (16 devices max)
% L$ `; E3 k$ l a3 O2D Graphics Processor
; P. R2 z5 X# B0 |- L■ High performance 2D graphics controller& w9 }0 I3 O: ]
■ Alpha BLT
3 [" F$ Y8 G' \- a6 M1 H( w8 U% e■ Microsoft® Windows® GDI GUI acceleration:
" H: O9 {# p9 b- \6 {$ O5 N9 D— Hardware support for all Microsoft RDP codes
, Z6 F; Y; K b8 n+ S$ k" d# H■ Command buffer interface for asynchronous BLTs
" {0 R) U* d6 V5 b$ @( `" R9 S3 \■ Second pattern channel support9 Y' {" |0 q9 u+ ~( t( T: k2 W
■ Hardware screen rotation |
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