You must be sure that, 6 O: q7 B4 [$ o; s1. your design output meets standard SVGA HSYNC/VYNC timing 5 @; Q$ a! A* J% X& B$ x2. You must also set constraint on the ISE project, and check the timing report after 3 M5 M+ B8 |% b! K+ s
the P&R is done. (also called STA timing report)4 }. i( b0 C0 x g9 o6 e0 m* P
3. Sometimes, you must check the board, and I/O SSO issue(signal integrity....)