Design of High-Voltage-Tolerant ESD Protection ' o5 H' w& r8 H& G. c) d& ZCircuit in Low-Voltage CMOS Processes/ m3 ^1 C) J4 p% O3 l
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2009 4 k2 c7 X; C1 Y: D ! M! ]+ I% M; y* P0 I; ~# D; D