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IV. CONCLUSION4 ^* ^, y4 t* w# L# p
The designs with 3-stage-inverter and 1-stage-inverter: c7 j" O( P2 Y3 [& p( S: F
controlling circuits have been studied to verify the optimal% ?5 V. X( l6 A0 i
design schemes in NMOS-based power-rail ESD clamp
: ^5 b! P; C" f3 x: x7 qcircuits. In addition, two ESD clamp NMOS transistors,9 L4 C" `3 c+ s
having snapback and no snapback operations, also were codesigned. z9 A" N6 K! s! T; v
with different controlling circuits to realize the
2 K2 Z7 a" `! j, J2 ~* _. Kimpact on their required performance. According to the2 P+ [% ?! O' A. B
experiments and analyses, the 3-stage inverters can slightly, G" n. V/ }7 B& q2 Z7 v
increase the ESD robustness, but they also can dramatically8 c" i2 U, }. Z2 Y: q+ r
sacrifice the mis-trigger and latch-on immunity. The 1-stage
% z8 {1 S" O S5 H" {) ~' Binverter should be an appropriate and reliable candidate for the
! K" I* ~: `, J1 Npower-rail ESD clamp circuits. |
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