Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
( j: f* h! r: Q( Y7 `Circuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
% r! G7 O1 l8 ~! X
注意：内容有一定深度，初学者可能看起来有些困难。

遊客，如果您要查看本帖隱藏內容請回復

semico_ljj

IV. CONCLUSION
6 p3 o7 ?* U* ]2 I0 WThe designs with 3-stage-inverter and 1-stage-inverter
" @, a6 g8 O) ?( |& _; w- Scontrolling circuits have been studied to verify the optimal
+ q& J$ p' W" P4 Z6 G# \design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
impact on their required performance. According to the
1 d+ E: G. V$ _* r% h" Gexperiments and analyses, the 3-stage inverters can slightly
; }( F/ }. T) A: J  Nincrease the ESD robustness, but they also can dramatically
1 o* I6 {5 C; C1 Ssacrifice the mis-trigger and latch-on immunity. The 1-stage
4 X& ~& j& M& Y  X9 G* f3 |inverter should be an appropriate and reliable candidate for the
& q7 L: E  @; |' F8 N; a9 u5 k2 C- m* }power-rail ESD clamp circuits.

aicder

very good!
* t& w" c3 g' U6 X5 @DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD

kevin5461

好東西~~謝謝這位大大的分享~~~~~~~~~~~~~

layes2

還要回復啊。希望能學到一些東西，謝謝！

jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！