Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism in a 0.13-μm
: n+ V+ e5 l# C& t; {, ?5 BCMOS Technology
5 I, q, j5 |1 w& x! {
Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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semico_ljj

IV. CONCLUSION
5 E8 d0 b* K+ B4 y* A( h+ B0 KThe designs with 3-stage-inverter and 1-stage-inverter
6 `' b  X, p4 ^, b+ bcontrolling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
' q+ D# n" ^, l' p7 g) P# }9 phaving snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
) x* C6 x$ `* Y8 X1 G: limpact on their required performance. According to the
3 Q; c/ [3 U* u! Zexperiments and analyses, the 3-stage inverters can slightly
7 v9 N, r% @) A  j" f0 ?( Eincrease the ESD robustness, but they also can dramatically
3 m  l# c5 d5 [1 I( \sacrifice the mis-trigger and latch-on immunity. The 1-stage
2 l6 g, ]9 |8 e. b% c3 Binverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.

aicder

very good!
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kevin5461

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layes2

還要回復啊。希望能學到一些東西，謝謝！

jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！