Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
+ t5 m) ^! f% s5 t. p/ w! a1 NCircuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology

Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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chkd002

正在學這方面的知識，多謝分享好東西！

jstsai

very useful, Thanks for your sharing...........

layes2

還要回復啊。希望能學到一些東西，謝謝！

kevin5461

好東西~~謝謝這位大大的分享~~~~~~~~~~~~~

aicder

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semico_ljj

IV. CONCLUSION
: R$ f! i# n8 z) U) y5 ^$ fThe designs with 3-stage-inverter and 1-stage-inverter
# [1 w" e  l" O5 Gcontrolling circuits have been studied to verify the optimal
4 N1 O! d; j- F1 F" ?, Tdesign schemes in NMOS-based power-rail ESD clamp
/ B, @; @0 a0 u( v$ K+ T5 Ncircuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
/ a8 Y3 _$ h3 e8 B  hwith different controlling circuits to realize the
2 g4 m6 x- h$ b2 K1 F( I2 j9 rimpact on their required performance. According to the
2 t6 u0 K1 c7 V" l, W( Dexperiments and analyses, the 3-stage inverters can slightly
( @4 B1 e: a  [! Rincrease the ESD robustness, but they also can dramatically
- v; d0 f6 b0 H/ d- Dsacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.