Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
+ W& @1 i5 I& n, F' BCircuits with Gate-Driven Mechanism in a 0.13-μm
; \7 ?6 Q' q7 h: QCMOS Technology

2 r3 V3 b8 T- w& k3 b/ l# S+ oAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
, M* ^4 c, x1 W' U8 `2 N; A  fdesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.

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chkd002

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jstsai

very useful, Thanks for your sharing...........

layes2

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kevin5461

好東西~~謝謝這位大大的分享~~~~~~~~~~~~~

aicder

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  Q3 I) o5 f& i! s+ _DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD

semico_ljj

IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
% o8 Q; \/ v! A- K' t2 y( icontrolling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
5 D  |7 y$ T2 Chaving snapback and no snapback operations, also were codesigned
- [. O' \! H# \% R/ B5 x% Z1 x6 ~7 y4 _with different controlling circuits to realize the
) A% N) U$ {. X9 zimpact on their required performance. According to the
experiments and analyses, the 3-stage inverters can slightly
# f% I% j! O  v  xincrease the ESD robustness, but they also can dramatically
sacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
3 Z6 l5 E& V# L9 Bpower-rail ESD clamp circuits.