Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
Circuits with Gate-Driven Mechanism in a 0.13-μm
0 {4 ?5 v8 ^8 |$ ^7 Z; ]# R* VCMOS Technology

Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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. v/ I, D; {9 W( a+ l9 K注意：内容有一定深度，初学者可能看起来有些困难。
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semico_ljj

IV. CONCLUSION
/ K, C2 N7 N* a0 [6 yThe designs with 3-stage-inverter and 1-stage-inverter
) V* N8 c2 x' }. Q/ t* Mcontrolling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
& V. K5 K5 L- G5 ?: Y. }$ Ehaving snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
impact on their required performance. According to the
experiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
sacrifice the mis-trigger and latch-on immunity. The 1-stage
* P+ u. Z0 Y+ p3 b" C5 G3 U$ K* F" Cinverter should be an appropriate and reliable candidate for the
0 H& @' \7 m( Y: O* r9 tpower-rail ESD clamp circuits.

aicder

very good!
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kevin5461

好東西~~謝謝這位大大的分享~~~~~~~~~~~~~

layes2

還要回復啊。希望能學到一些東西，謝謝！

jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！