Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
/ H/ Y3 V- ^" u$ ICircuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology
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; B! `$ r) B8 o; qAbstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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semico_ljj

IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
; O+ C& r1 M4 V! Scontrolling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
' H& R1 |$ G* i/ Mcircuits. In addition, two ESD clamp NMOS transistors,
having snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
impact on their required performance. According to the
experiments and analyses, the 3-stage inverters can slightly
3 |0 D6 a  P5 X8 \! pincrease the ESD robustness, but they also can dramatically
sacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.

aicder

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kevin5461

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layes2

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jstsai

very useful, Thanks for your sharing...........

chkd002

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