Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
( e# E# d7 v' n+ B  [) eCircuits with Gate-Driven Mechanism in a 0.13-μm
CMOS Technology
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Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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chkd002

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jstsai

very useful, Thanks for your sharing...........

layes2

還要回復啊。希望能學到一些東西，謝謝！

kevin5461

好東西~~謝謝這位大大的分享~~~~~~~~~~~~~

aicder

very good!
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semico_ljj

IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
design schemes in NMOS-based power-rail ESD clamp
circuits. In addition, two ESD clamp NMOS transistors,
1 j  v( p5 P. D* o' `* ?, Chaving snapback and no snapback operations, also were codesigned
with different controlling circuits to realize the
$ N( U; p$ p' }$ Dimpact on their required performance. According to the
- Q' p* o# D3 X! [) W& `+ ~- ^1 Hexperiments and analyses, the 3-stage inverters can slightly
3 j9 b: i8 y/ j# c, b; `8 t$ Vincrease the ESD robustness, but they also can dramatically
sacrifice the mis-trigger and latch-on immunity. The 1-stage
' i3 |4 {, Y9 Y5 pinverter should be an appropriate and reliable candidate for the
power-rail ESD clamp circuits.