Stanford_Mark Horowitz_Digital MOS Integrated Circuits

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Lecture 1 - Intro and Modeling   
Lecture 2 - RC Modeling and Calibration        
4 @. |% o- d% o1 ?3 NLecture 3 Memory Design   
8 t+ l# L/ O  U, j) v7 [' a# d- C2 GLecture 4 - Delay Optimization and Logical Effort   
Lecture 5 - Decoder Optimization   
! B' I, @8 O- b* rLecture 6 LE in the Real World   
Lecture 7 Lower LE Gates   
Lecture 8 - Low Field MOS Transistor Model   
8 [, D$ n1 ~* n3 rLecture 9 - High Field MOS Transistor Model  
Lect 10 - Using MOS Models   
/ t* v8 }& p. T( [Lect 11 - Cap Models   
Lect 12 SRAM Column Circuits   
3 W$ |5 S7 U  f0 M5 G' ~; j" J9 QLect 13 What Makes Gates Digital
Lect 14 Diff Pairs - Current Steering Logic
Lect 15 - Static Sense Amplifiers   
Lect 16 MOS Matching Clk SenseAmps   
3 n# I7 C: W2 C5 c+ ?# lLect 17 SRAM Noise Margins / Noise   
Lect 18 - Timing Gen and Array Partitioning   
Lect 19 Adv Clocked Logic   
; M& v8 j- P1 n3 j" {# N/ ?Lect 20 Low Swing SRAM   
. ?) d1 s3 B2 m# wLect 21 - Introduction to Solid State   
Lect 22 Threshold Voltage, Leakage and Tunneling

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