Stanford_Mark Horowitz_Digital MOS Integrated Circuits

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Lecture 1 - Intro and Modeling   
Lecture 2 - RC Modeling and Calibration        
* a+ g: C8 P9 {. \5 b: \Lecture 3 Memory Design   
6 v0 c) ^. l/ X) ^5 TLecture 4 - Delay Optimization and Logical Effort   
! ]* n, h% g: v6 ?" z9 J; cLecture 5 - Decoder Optimization   
; @, U& E% ]; R: @3 \* eLecture 6 LE in the Real World   
Lecture 7 Lower LE Gates   
8 S' n5 B% P; `( b" c! nLecture 8 - Low Field MOS Transistor Model   
Lecture 9 - High Field MOS Transistor Model  
Lect 10 - Using MOS Models   
Lect 11 - Cap Models   
5 H# p7 g! B; b0 T0 k. e2 ZLect 12 SRAM Column Circuits   
2 [+ b# a' _: W- F" \Lect 13 What Makes Gates Digital
& d9 ~) y4 v$ n5 c/ vLect 14 Diff Pairs - Current Steering Logic
Lect 15 - Static Sense Amplifiers   
Lect 16 MOS Matching Clk SenseAmps   
0 n, h" D" k8 z+ A/ SLect 17 SRAM Noise Margins / Noise   
4 V, P; y7 z& Y' S; W: a" wLect 18 - Timing Gen and Array Partitioning   
1 [1 V# Y3 e" a/ r  ?6 m6 Q& T% m9 O. ?Lect 19 Adv Clocked Logic   
; v, \* _7 F7 t6 W4 ~Lect 20 Low Swing SRAM   
9 _4 s9 Q, I, f% c) U, yLect 21 - Introduction to Solid State   
* i# M, f# W+ D1 ^0 kLect 22 Threshold Voltage, Leakage and Tunneling
5 V& }, w' [) `7 N2 b& Q2 {3 M
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