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Lecture 1 - Intro and Modeling 2 @ p- S2 B: f* k" g6 i8 h' b
Lecture 2 - RC Modeling and Calibration " X! x/ T9 k9 g
Lecture 3 Memory Design 5 ^; w% y/ H" I8 ^
Lecture 4 - Delay Optimization and Logical Effort / D9 Q! \6 x2 x$ \: }* b
Lecture 5 - Decoder Optimization , z: _$ Z% t9 Q" d+ ]
Lecture 6 LE in the Real World ) D' C7 z0 W) S7 G$ N y9 j
Lecture 7 Lower LE Gates
: m( k2 a1 @$ RLecture 8 - Low Field MOS Transistor Model
8 C2 e# E$ }! K1 jLecture 9 - High Field MOS Transistor Model
( X6 [$ z; y4 Z8 nLect 10 - Using MOS Models
2 @8 U, V/ n- T' S: Y$ m* `Lect 11 - Cap Models
! H+ Z; I8 A5 |; [6 yLect 12 SRAM Column Circuits
- o' z5 L# C0 I% E. h5 fLect 13 What Makes Gates Digital; Z# \ `' v/ [0 F6 Y+ G) |
Lect 14 Diff Pairs - Current Steering Logic; _$ q! B% F. |. W
Lect 15 - Static Sense Amplifiers 3 C2 U$ f& B( q' C
Lect 16 MOS Matching Clk SenseAmps
* ?! h' v# u; W" Z7 ^2 ALect 17 SRAM Noise Margins / Noise 2 C9 x) |0 V9 d3 \" M/ e2 k
Lect 18 - Timing Gen and Array Partitioning 0 G8 y6 V$ s: l. i$ ?! n
Lect 19 Adv Clocked Logic / B# S, ~; k# C' S- ^ Z* b E. `1 j
Lect 20 Low Swing SRAM & _* q8 s: q, U2 Z% b4 k+ J
Lect 21 - Introduction to Solid State
! k' a$ A' @, `" B2 D! Y6 ILect 22 Threshold Voltage, Leakage and Tunneling
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