Overview on ESD protection design for mixed-voltage I/O interfaces

semico_ljj

Overview on ESD protection design for mixed-voltage I/O interfaces
with high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology

Introductory Invited Paper
% B$ m2 p  l4 n. Y4 j2 MMing-Dou Ker

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