Overview on ESD protection design for mixed-voltage I/O interfaces

semico_ljj

Overview on ESD protection design for mixed-voltage I/O interfaces
) D% i3 a* j. Qwith high-voltage-tolerant power-rail ESD clamp circuits
. E2 |* a1 y  W2 P, Iin low-voltage thin-oxide CMOS technology

! g# Z( B" r1 a9 IIntroductory Invited Paper
: p7 A9 ?# L8 N! ]/ q: ?- f; FMing-Dou Ker

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ulysseslaii

goodgoodgoodgoodgoodgoodgoodgood

heyunpro

goodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgood

cedric761193

The ESD is easy implement but difficult to design.