Overview on ESD protection design for mixed-voltage I/O interfaces

semico_ljj

Overview on ESD protection design for mixed-voltage I/O interfaces
# m- X# j7 q7 w7 P6 Dwith high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology
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8 U/ `% d7 m3 T9 o4 tIntroductory Invited Paper
Ming-Dou Ker

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ulysseslaii

goodgoodgoodgoodgoodgoodgoodgood

heyunpro

goodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgood

cedric761193

The ESD is easy implement but difficult to design.