Overview on ESD protection design for mixed-voltage I/O interfaces

semico_ljj

Overview on ESD protection design for mixed-voltage I/O interfaces
with high-voltage-tolerant power-rail ESD clamp circuits
7 O* i; A! a, t7 Tin low-voltage thin-oxide CMOS technology
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' `+ T  G7 o) |% {3 r$ \Introductory Invited Paper
  f. D: n$ d; z5 B- rMing-Dou Ker
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cedric761193

The ESD is easy implement but difficult to design.

heyunpro

goodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgoodgood

ulysseslaii

goodgoodgoodgoodgoodgoodgoodgood