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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用0 C0 {# P$ A6 t" `4 `2 L
Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
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Dummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance % O" f k4 I5 Y. C% r! n
Extraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer
" l5 F. f( r: l5 K' H' M( e# R/ L% s$ _dummy, 為的是在CMP process時,有較佳的均勻性:3 q1 k2 t' {: Z8 {* s
Dummy(or fill) metal is introduced in the interconnect process flow to enable uniform
8 ~1 X! t8 w& ~ thickness control in the CMP process. Dummy metal needs to be treated as floating metal 7 }9 L$ f( B: |+ |$ ^( g
unless it is intentionally connected to a constant potential. Floating dummy metal ' y9 k5 {( R4 [: [! o1 q1 z
essentially acts as a capacitance divider.
$ U. G7 o3 R0 U7 o/ ^* h. q$ B另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆/ O4 V% s/ G) _4 g$ S, X
mos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保
+ f3 [5 o/ j0 p- O主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部; C0 D- d% J k1 f2 h y" I1 ^- ]
份).以上是我自己的想法,歡迎各位先進指教 |
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