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我在之前的公司有lay過double guard rings,內圍是用PTHIN guard rings,外圍是用0 b% g. a @) q- O C
Nwell+NTHIN(甜甜圈結構).主要就是用來防止noise,那時是圍在Oscillator外圍.
6 | J% k# l0 E* ~6 ?8 h# d1 P0 ?. q1 e6 v7 k O7 \$ k
Dummy的話,不知道你指的是那部份?? 引述一篇paper " SmartExtract:Accurate Capacitance
! N l5 v) c5 ]8 W+ W& r; t" D, nExtraction for SOC", 這裡提到的dummy是指layout完成後,在每層layer空曠處,補上同一layer
1 N; B {) H; @dummy, 為的是在CMP process時,有較佳的均勻性:
2 X% K* f$ X4 F! I- S5 W3 hDummy(or fill) metal is introduced in the interconnect process flow to enable uniform
8 y# M' X9 ]2 z thickness control in the CMP process. Dummy metal needs to be treated as floating metal " D G: v" a/ u& h
unless it is intentionally connected to a constant potential. Floating dummy metal
. J* X6 o, O1 @essentially acts as a capacitance divider.' m0 D+ E# g2 x- K4 V" V5 C
另外有一種dummy, 之前我在做analog layout時,會在需做match的mos旁,故意lay半顆或整顆
( |2 O5 `5 c+ ]) [, C# U+ t& y/ ]mos,除了你寫的那些原因,我想是因為實體mos的邊緣不見得是像layout般的四方形(what you draw is not what you get),可能是梯形或不規則多邊形,製程上很難做到如此完美,所以為了確保& r4 t( V U) p& y
主要的mos的完整性及對稱性,在mos旁再多加dummy mos(不要讓主要mos成為最邊緣的部, {1 x! e( g$ e. h! l) m. ]/ T
份).以上是我自己的想法,歡迎各位先進指教 |
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