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這應該是APR的論文
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- Z# s1 ~/ x$ ~' { V. QAbstract:9 p; q" P9 k9 t
Parasitic interconnect corner methods are known to 8 K1 F3 U7 [; {7 _
be inaccurate. This paper explains the sources of their errors and
7 b- ^5 E8 R, @: ~' bshows that errors in excess of 22% can occur in the predicted
9 q8 o! J/ ?& tcorner delays of a multi-layer stage in the presence of process
: J( Q( g: b: U q. Z( pvariations. It is shown that exhaustive corner search methods are# \% T) _& P4 K2 }- p
infeasible in practice as they have an exponential complexity in
6 y6 |5 I* _. ~terms of required SPICE simulations with respect to the number* d+ Z5 o1 L, `
of layers a stage is routed through. This exponential complexity
$ c1 u3 |# ~8 Dis reduced to a linear one with a new simulation-based search
# D- a4 e8 h- W: e( G+ ?9 F& M, w8 \% ymethod with the aid of stage delay properties. The ideas behind& O" c6 D0 @+ [' A# Z1 i
the simulation-based methodology are shown to be expandable. m4 \- O* ?9 @- y2 ~7 N
to an analytical-based multi-layer performance corner location1 x, g0 N0 ^' b5 [1 s: G8 X0 m9 V
methodology. The simulated best/worst case delays based on these
3 K4 s% o' }, A6 F. a+ b& u9 P0 @analytical corners produce errors below 4% as compared to the
( J O: r$ B+ A1 [exhaustive search simulation based method.
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[ 本帖最後由 masonchung 於 2008-4-22 12:01 AM 編輯 ] |
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