(ESD) Failure Mode, Relibility and case study.

yhchang

8 Failure Modes, Reliability Issues, and Case Studies 228
: ^5 l( }* l$ V( m/ ~6 ~& A8.1 Introduction 228
5 |5 A& @) J( t; j* c& |& X# P8.2 Failure Mode Analysis 229
8.3 Reliability and Performance Considerations 238
0 _$ z& h7 t: x* n8.4 Advanced CMOS Input Protection 239
8.5 Optimizing the Input Protection Scheme 242
( V5 U6 H* Q7 ]' T: q& m8.6 Designs for Special Applications 249
: L) Z" _3 b& o' y! g. J& N8.7 Process Effects on Input Protection Design 253
8.8 Total IC Chip Protection 255
" \- [) F: U$ M3 b( n, Y$ t8.9 Power Bus Protection 256
& ~3 r2 b+ a6 X  F. V. a# @* j7 c8.10 Internal Chip ESD Damage 258
9 G$ O$ P# |# Z4 W" R1 f5 }. }8.11 Stress Dependent ESD Behavior 263
8.12 Failure Mode Case Studies 267
1 @( j5 a+ a1 i) J8.13 Summary 271
: N  Q+ i" \( ^+ V: TBibliography 272
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