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8 Failure Modes, Reliability Issues, and Case Studies 228$ V# ~) J' \- b( [, r$ G* Q3 B5 s ]
8.1 Introduction 228
0 y" |2 o9 B) ~ k1 n( ^4 K8.2 Failure Mode Analysis 229
2 ]* m% Q w" U) o# E/ c, K/ F- e8.3 Reliability and Performance Considerations 238
- F8 `* G) y- x2 s, U5 K$ Q. l8.4 Advanced CMOS Input Protection 2396 V+ G/ r6 W" \; h
8.5 Optimizing the Input Protection Scheme 242* }, V5 |4 N0 F$ \/ K _& ?
8.6 Designs for Special Applications 249# W0 Q0 C# Y; w Q/ v- Q
8.7 Process Effects on Input Protection Design 253
( b$ ?$ t: E6 o/ k: t8.8 Total IC Chip Protection 2553 t8 z0 a( Y+ k* Y) ~* L0 j+ {
8.9 Power Bus Protection 256% |% Q5 ~" [3 Y1 V
8.10 Internal Chip ESD Damage 258
$ {* ^4 y3 e8 \' u1 H% E8.11 Stress Dependent ESD Behavior 263
$ o4 U; Z+ y9 \5 } M3 Q8.12 Failure Mode Case Studies 267
) S4 d& g6 i' s' s0 f K8.13 Summary 271; A! |& m: Z, h, s5 E+ E
Bibliography 272
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