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8 Failure Modes, Reliability Issues, and Case Studies 2284 O; E7 @( R8 J5 f% U) z
8.1 Introduction 228" e2 d" M1 W" h4 W
8.2 Failure Mode Analysis 229
: u# b" n- p! w" m# n, T" e8.3 Reliability and Performance Considerations 238
/ u5 ^( ~+ w k8.4 Advanced CMOS Input Protection 2393 c9 B/ K& |8 g' X- f
8.5 Optimizing the Input Protection Scheme 242
5 o+ ~( a5 y& @8 ]. R1 S L8.6 Designs for Special Applications 249
. j! e2 e0 c j* Y% E$ f8.7 Process Effects on Input Protection Design 253( M7 A4 K; e) m0 H4 ]5 L+ n
8.8 Total IC Chip Protection 255
6 w/ J9 h& A, e. R. I8 g8.9 Power Bus Protection 256
3 [$ I0 m3 T! G% o2 f2 _/ E" N7 g8.10 Internal Chip ESD Damage 258
: S2 d, U9 I2 v' S D' R* O, s& P8.11 Stress Dependent ESD Behavior 263
; ?; \/ n/ e& [; X4 V# s8 ?8.12 Failure Mode Case Studies 267
% B% I1 b7 i: \) x" `8.13 Summary 271* w5 S# R+ \9 y( J4 W
Bibliography 2723 Q+ G* r$ f0 h
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