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8 Failure Modes, Reliability Issues, and Case Studies 228" L" f' u w+ H' ^: @" M
8.1 Introduction 228
4 ~0 K0 a; v2 Y2 l, M1 w8.2 Failure Mode Analysis 229
! J, \: c. p G. Q0 i* a8.3 Reliability and Performance Considerations 238
. o0 x$ X" G0 q/ t8.4 Advanced CMOS Input Protection 239
$ H! Z+ K/ K+ t( W6 R8.5 Optimizing the Input Protection Scheme 242
5 y% s5 M6 R; O# H8.6 Designs for Special Applications 249
6 w5 ?, I3 y [) j3 G! v8.7 Process Effects on Input Protection Design 253# n$ _/ P+ z5 ~; ~0 H; S
8.8 Total IC Chip Protection 255
7 i* Q! E0 \* ?) x+ ]8.9 Power Bus Protection 2569 b" N* N3 ]+ e( D; j$ e- e. S
8.10 Internal Chip ESD Damage 258
8 P9 w/ \5 I4 `" s2 b. ^9 W8.11 Stress Dependent ESD Behavior 263
! D( F( G |* ~. _. |# Y6 Y9 z8.12 Failure Mode Case Studies 267
; @8 @! Z, N5 d' B, O8.13 Summary 271
- Y. I/ Y9 K5 VBibliography 2724 e) A1 `3 U5 ~6 t; V8 t
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