For ESD test (HBM). {1 a4 u; y; U& @ H
The following are the test combination: 5 j7 C8 \) t5 e# J2 ?9 b. k1. Power to Power' R! @* o) H9 z/ P/ a
2. Power to Ground+ S! o0 \4 X. {9 ]
3. IO to Power. K8 x( p% v& V4 ^
4. Io to Ground3 g2 _+ C* W' i2 ?. m; x
5. IO to IO * A5 B' C6 d( h(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.) 0 D) s9 ~: y7 @8 z4 K9 E& P. D. x2 }, Z
the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG); q* i J9 d, y9 p5 f# R2 I
For example: You have IO1/IO2/IO3/P1/P2/G1 . A6 M) v/ O" g' C6 T0 p2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval) : Q1 v5 S2 ]. I( \. O1 hSo for high pin count it will take a lot of time. But it won't take more than a week(for one chip). - I4 n W5 o% o2 F" L6 K$ I& a p' P' g6 ?% V1 k7 ]
For your reference.
thanks wesleysungisme for your answer. 3 f @" R; x, J, N1 Kas our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming. * u0 f2 t' {. v( M2 Qand there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.