靜電放電測試

ritafung

剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？

m851055

竹科閎康科技有此業務
9 ?. F% a  b# a, H2 h' R: R電話在網頁就查的到了.......................

cuban487

很多實驗室好像都有,但都在台北.
0 }# S, u" _) L3 q) b* K3 n  p儀特好像就有可以去查ㄧ下

kyyyyyykimo

目前新竹地區有"宜特"與"閎康"兩家比較大
我的建議是去閎康，會比較適合。
因為我本身工作性質也是有接觸到ESD測試
測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE
/ x; |( d1 M( w( H在Zap的次數明顯比軍歸來的少了。

ritafung

my company is pursuading to MIL-Std ...
+ l. z* ~% t5 w. u. N* Oactually any company need MIL-Std? Our application is not for military purpose....

wesleysungisme

For ESD test (HBM)
9 C# G8 ?; B1 rThe following are the test combination:
7 r+ c' Q* F9 P2 s# W5 |" n, p- b* Q& q1. Power to Power
2. Power to Ground
3. IO to Power
4. Io to Ground
5. IO to IO
5 K! y+ ^( b9 A6 M0 d(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)
) g1 x9 q, ^' C  e
the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
8 P0 j7 R1 T$ B" KFor example: You have IO1/IO2/IO3/P1/P2/G1
5 c7 h' D( ^4 T; c) p( @, u' T0 F/ ^2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip).
" J  P- R: _4 m9 a5 I0 w
For your reference.

f5882077

樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??
) A& Y6 }! d' T  n5 [3 n有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~

ritafung

thanks wesleysungisme for your answer.
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming.
( S; G  o: G3 I  }3 D8 j# \$ S) [and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.