For ESD test (HBM)9 ]5 \) V9 Q0 r. t
The following are the test combination:! P6 ^ v" X) A: X' Q9 @; M2 `$ o
1. Power to Power 5 u& F' K( D* `: {$ p2. Power to Ground( x5 T9 \( H4 e9 m
3. IO to Power6 N1 W* X* s; j& k6 l
4. Io to Ground0 ~/ |- @7 @( T) C
5. IO to IO % U- Z) u# `" j(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)3 F; R6 P! z7 F" W0 Y
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the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)1 k( Q2 d, _! H8 e5 q
For example: You have IO1/IO2/IO3/P1/P2/G18 C# o% F4 _% G6 m% D
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)9 n3 x: ?) `7 b- L& l5 Z
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip). 0 v: p3 p7 D0 j7 m/ v - r! y5 d$ E' ^! yFor your reference.
thanks wesleysungisme for your answer.4 S1 m8 x1 K2 d
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming. * o0 T( F, |* J: t G( Q1 `$ `+ ]and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.