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*Objectives# `$ D/ `. Y( m u
After completing this course, the student will be able to:
I2 V0 Y& ]0 M7 n2 A7 @' e; BDescribe both the feature enhancements of the V5 over the V4,4 }% D, ]: J8 Z$ a0 I
and
& M9 S) F7 O/ m INew architectural features of the V5
/ g4 U+ o+ N* {' Q. P2 _Have a fundamental understanding of how these features can be
2 d$ k3 N' c0 Xleveraged to bring about timing closure.) n5 x, O) ], |) H' N4 T, V
*Agenda7 D: E$ x6 g! v. `2 P; P, k. M8 I; L
Overview (15 minutes)
6 F9 y) ]0 U0 t$ E9 I) A: G0 A1 uBrief Description of Differences between V4 and V5 (30 minutes
' @- P4 W6 [2 |9 e* ]V5's new PLL and Use with DCMs (45 minutes): u* s2 t, E" J$ x3 C1 P
Lab 1 – Introduction to the PLL/Architecture Wizard (30) R# _2 V) g* ]2 b5 u
minutes)
+ z$ o! T% Q1 l3 h1 Y4 \# CImproved Features in V5 (30 minutes)" k: ~- p1 m) D* R: X& e2 y
Lab 2 – Leveraging Improved Features (45 minutes) |
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發表於 2008-3-26 00:28:20
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