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LOAD SDC FILE時
- S2 v6 H8 x% B u1 l2 j: ~Astro 訊息
* t! }( f; O7 W0 T---------------------------------------------------------------------------
5 f U" n7 _, l. X7 r, W% ZInfo: starting Tcl processing
6 k4 P& |" Q/ c' ? w3 _Info: building design object name tables
8 x6 P; [, ~/ G1 L% _& VWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)$ N& B: q$ F5 q: y* m3 z) h- y
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)# X( X4 m" V+ F: q
/ a2 ~ s1 S1 r. f----------------------------------------------------------------------------
9 g6 b1 N' f+ b$ pSDC FILE
8 b# b+ h i) D0 M7 Z1 n6 ]
: j' U, C9 S) Y+ Aset_multicycle_path 9 -through [list [get_pins \4 A# D' i. A# H% {% q1 m2 K
{TOP/test/mul/A[26]}] [get_pins \
) ^4 v* {! k( s& o* @1 x{TOP/test/mul/A[25]}] [get_pins \) T5 C. D9 Y5 V5 T9 F6 G
" S+ E8 b3 @2 t+ b) z# h' Q
q- N4 l% H( }( }5 H
-----------------------------------------------------------------------------) }* q8 D3 E: f; U3 O
Verilog File7 ~) R9 G8 |# P- }+ y$ T
$ m. a8 Q5 ?; U0 a uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(+ K6 x' u% l4 }& P! W
icwAeYfNum[18:0]), .C(ae_avg) ); |
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