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LOAD SDC FILE時7 c; G! D8 e$ |" y
Astro 訊息1 P0 z$ K& x P. D
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Info: starting Tcl processing, ?8 y! ?- \& j* ~7 e" L
Info: building design object name tables - x5 f# K( q% [6 ]
Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)- ]) u6 v/ `2 e: ]
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
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/ @. a/ ~! M' ]: @5 F0 {7 z' S----------------------------------------------------------------------------, A9 W. t$ J0 Z
SDC FILE
# B- W6 W& Y* p6 B; d1 {9 g9 i1 U( z. a4 B5 g; }+ d
set_multicycle_path 9 -through [list [get_pins \7 T& W+ H( \$ ^; v9 `
{TOP/test/mul/A[26]}] [get_pins \
% ]) |% s, D# X( N{TOP/test/mul/A[25]}] [get_pins \, s" C/ ~$ }3 f E
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-----------------------------------------------------------------------------
) ~$ Q% ]) a+ M8 j2 ?4 QVerilog File; x5 Z4 W. O7 \. O
; J$ [* x4 u1 ~' s uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(& V$ a$ N0 ]8 j4 r4 |8 e g
icwAeYfNum[18:0]), .C(ae_avg) ); |
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