Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

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Contents
$ y7 S4 m2 M) dList of Tables
( D, P( n7 o9 p8 n) G9 P) h* [) RList of Figures
- [6 H* Z) F4 R) NSymbols and Abbreviations
0 e5 p0 o6 p; d" N" kPhysical
1 Introduction 1
2 V" O, ?; M( [& Y* J1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
' D& }. O1 j* E% \, X' B: l1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ADCs in Nanometer CMOS Technologies 3
( d: y1 w/ H) R2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
8 {! p" n  z( I8 P2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
7 o' L3 w: B' \: p2 m2 S! J2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
/ t% _$ W0 z# ^! F2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
5 W# z) q, H8 |1 t+ f2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
/ v& p5 w& U( }( B( E0 }. k2 P2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
/ I2 t: m5 [' \* Bvii
2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
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  E) G/ H* b7 c8 p! f; A! ~9 [. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
9 J; ]1 O  w0 |) J) ^* k. d0 YCONTENTS
9 Q) z6 D: t; f1 G+ }7 X2 y6 G2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Principle of - ADC 19
3 _5 D3 m5 y9 x7 x- ]3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
8 N! A- t) x' v" D2 e3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
# _7 _- u$ y: G# M2 G3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
$ {4 Y( B# @2 M3 @) A3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
( h' F1 L7 D& q3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
9 ?+ I/ i+ z6 z, M5 ~3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
, {5 f- K2 Q" L0 g5 i6 E4 V" o5 W3.4.4 Performance Comparison of Traditional - Topologies . . 46
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3 N0 S0 ]; K7 n, g( h; E2 N, v4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
2 _) O) g4 U$ q+ `Level Approach 47
! O( c0 |& ~) W, i, [) X7 X; p4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
# L8 o) B. V$ j) L; P8 G+ _4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
+ t  `# D5 J; m% d. G1 D3 p4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
% `- S7 u2 O% y, v4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
; ~/ D2 A4 e! |/ q8 R4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
; t* B4 c* i* B! n4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
$ P+ {6 U! K( h0 ]+ {4 ~1 {4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
) F# G2 z1 {, h  O: J4 C: u4 M  V4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
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4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
+ W- C, o( s; |: S. W' f4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
2 X* A8 u$ P% J8 o8 y7 r/ E4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
8 @* A5 s0 B+ S- [4 N4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
4 R6 F6 ^2 m: s  K, o- R4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
: i5 q6 }. K8 G9 k' {CONTENTS ix
CONTENTS
/ l0 w0 N% F: ]! E6 A8 Z6 Conclusions 149
Bibliography 151
Index 157