Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
4 |. e. r. C9 W* xList of Tables
9 I! Y& o) w* a9 nList of Figures
2 r% C- N3 S! mSymbols and Abbreviations
) N, A% x8 P) C8 B: D$ q' o; LPhysical
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
% H/ E' b3 C7 `0 k6 }2 ADCs in Nanometer CMOS Technologies 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
% Y6 U' L6 i! S* V8 T; w2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
$ l4 Z2 b- s, C1 g/ l8 x2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
- O" R% l  X' `5 `2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
1 R8 n1 Q$ O! _1 |, Y1 q% L' a2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
. ~1 z6 N, Y( V6 k: C! H% t' a2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vii
2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 S7 B& V! H7 E1 ~5 M5 ]2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
4 _0 h( `7 c& T. R9 _  hxi
xiii
xxi
! G( ^! c+ B8 z3 Q9 p- u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
) L% A$ R" H1 T& B9 Q6 P' RDefinitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
CONTENTS
2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
' e$ n8 L* X7 Y0 m3 Principle of - ADC 19
, f4 W7 y3 G+ u# s: `3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
) [# S0 Z5 p! M3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
6 F% W1 B# @, ]' {; W' g; @3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
. ^, R" I7 L; p% z: [' Q( `+ K3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
1 w# e7 x3 c( Q0 V2 F$ M6 z5 M& `3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
2 I' X# W0 E+ |( b3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
2 W! ?+ O: ~$ Y0 G! _& x+ K0 v% V5 v/ S3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
3.4.4 Performance Comparison of Traditional - Topologies . . 46
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
) I- Z# _( E9 n' F& I$ Q/ JLevel Approach 47
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6 i5 q" K; d" b' C2 w, `4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
5 q- v! P4 E: ]4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
2 M" O9 j, A" ~2 N  p4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
9 r2 V: ^$ l/ n4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
2 U4 H2 d" X  d. S( Q1 x$ Q- w4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
9 H* h0 ]- \( }( t6 ~4 ~0 h4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
  U5 [" [+ Y: o4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
3 _, U; r# C$ D0 ?  L$ j% u  f% G9 K4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
) f  N  A- m. j' Q8 Y: Q! K  pviii
4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
0 b" n4 a8 g! h* g6 o4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
1 T) Z$ Y3 f% [: m% }) V1 V, T4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
3 M% O1 a1 k6 G+ J- K  u" P" l" T4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
$ M2 d5 U2 G/ T# m) p5 I( _CONTENTS ix
CONTENTS
6 Conclusions 149
+ ~: R/ z1 |, }$ ^0 c0 k) JBibliography 151
( ^* `3 X) G0 S4 BIndex 157

scan7510

看不太懂
可能還沒學過吧
. @: N) k8 B1 T1 S7 Q) ]現在只能單純推一下
/ v& F! J/ e/ f( o- P7 Y$ ~. x謝大大分享

deltachen

謝謝大大的分享~知識因分享而壯大！

jjam

感覺是非常實用的內容
感謝大大的分享~~
9 }! R8 ]+ }% y( N& J/ s6 ?/ N9 j希望能對SDM有所認識與了解