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Contents2 o; N3 z% G! V6 q9 m3 A% |- c7 Q& G2 }
List of Tables
+ \. I! ?$ x1 Q' Y rList of Figures% d3 q5 K, p/ `! R* i2 T# h# O
Symbols and Abbreviations
1 k* M8 _) J# UPhysical, m. A" H7 b5 I, e; |1 F5 E
1 Introduction 1
o6 a) |8 \+ W, o+ _8 v1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 ]0 H% A6 ~: ~$ K6 J1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, W, R. H. I7 N0 L2 D' q7 M, e/ m
2 ADCs in Nanometer CMOS Technologies 3
7 o7 Z* h2 P4 J- Z9 i2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 j$ y0 R0 c/ b2 P. W* J! A. P' k2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
5 K- \3 F2 |( f7 M+ [& ^' x2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4% N6 @2 [5 a+ K0 u) B R! `. @, i, W. |
2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 53 W6 p4 ]2 r8 e$ k. g+ x: W( Y% ~+ [) a- m
2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6& n" ]0 |& z6 p" _$ D4 v
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 61 s8 v7 W, e7 \9 f5 }% C# o$ g4 `1 ]
2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
" {8 r/ o; Y) E5 O- d6 U: {. C2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9; T7 _1 `" q/ S9 K0 X( P+ q
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10' ^! V: t/ Q* _4 b3 z8 B
2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11% M. s* ^6 \" A( t6 o4 O
2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
8 V8 S( F5 C) R4 e2 P- E2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13) T, ]) L8 H1 i
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 G! W( g5 M6 |- n' z: F
vii
4 u- t4 n5 a- e0 C, r# K8 A3 Q, `) ?2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
/ a" \+ N* Q% N7 A2 M# _( f2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 177 S3 M4 L) ?# w% R' C% [' g
xi
4 }+ r, @+ F, M+ Y Y0 C/ W' }xiii" e& F9 ~5 k5 _ ?9 w& A
xxi
, R; K# v- i, t$ I5 h* W. m' h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi$ ]% M k% D/ r7 ]: @
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
0 J5 f! ~% x+ [ g8 ACONTENTS1 g) n2 \6 b7 q8 x, _
2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 170 p: p# ^# X% \6 R
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
, C; u% D) k$ ^6 q; X2 z( S j7 Q3 Principle of - ADC 19
& B9 g) P4 h; `" M5 Z- S1 |* z5 I3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19. p! I' m1 \! w" ^# ^
3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
2 e% w* L5 f9 I! ]3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 244 ^5 w! n. w* a: X
3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 \3 z) c& d9 a, V, m3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26( f, K# C/ [5 z6 S0 ~, i% `
3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
. u, {9 @: W% K3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
) b, s2 W4 T6 z; [; z' ^3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
) `0 K( K* v. _5 n3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33% A) A9 S6 R$ `6 \, P
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
5 F' `, m h! ?3 e, l3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
* Q6 g8 m% P( t: |3.4.4 Performance Comparison of Traditional - Topologies . . 46
2 l" W/ [# J& f' R1 a3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 g+ R3 H2 C8 B' s3 |
4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
, c. m( D! ]7 ~7 Q& uLevel Approach 47
# s* B1 S5 C: o" k4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47) u+ ]; n" k% n8 l! s0 o1 q% N7 Z2 h
4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
# s. N S+ `6 d0 t5 j8 O, _4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
5 l) @) m0 E& N" a9 c4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
2 h1 S* f5 g" w& G4 n3 [% q' H4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54& K; o1 ^4 S+ Q7 ~0 }. j) l& \/ e( a
4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55& @& A L! t7 X/ q( f8 ~
4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66' b+ L* m( d) x) L- l
4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
, D5 X- z r: n- M- j) {% v4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
& Y( G9 U- L" }* Q7 O" a8 p0 R. X5 a$ s4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
* d7 i+ c7 y' h) U+ C9 S/ P, H4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
" q% L/ E! g) m4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
' _: j4 S, k7 j9 N# K* q2 l: d. q4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76# Y: ?- u- I% N2 w# g! `8 I, w
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76* c) F) {/ ?$ ?* G' O
viii
& E6 ^3 q* f5 Z4 | x# g$ a0 u2 q6 K4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
1 K" K5 \4 D; G( J- s4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82, d- B6 l. B0 F7 t
4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87# p) Z' n' l0 m8 n) v! m! a1 o
4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
# Z, L1 a8 @: A4 U6 p" ~0 ~4 g4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
- B, |3 I; v! o4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88% U/ Q& h3 }$ N, e
4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
8 Z! Z5 N& T3 b0 `4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 \/ |% Z' V; N- i
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System1 f6 }/ N$ S4 H. s) z5 j
CONTENTS ix
2 _& b. c+ t! T$ ~CONTENTS
+ M9 @# C' B# Z0 J2 E9 j; a6 Conclusions 149# D* x& F! C- j. ~0 H2 S
Bibliography 151( N2 `* ~$ h' y
Index 157 |
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