Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
1 Y, o7 e4 e3 O7 H' ?List of Tables
9 k8 w5 S, I8 z7 n1 OList of Figures
3 J5 c7 B  Q+ {7 A) P- t5 \/ qSymbols and Abbreviations
Physical
' ~; k; A6 e" }2 v1 Introduction 1
! z1 ]  _; |& X0 {( f1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
. c8 B4 S1 ], }1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ADCs in Nanometer CMOS Technologies 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
# E: \: ~- P) k, C+ ^3 X2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
1 t% M+ _2 P# d- H! D" J: E' \2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
; H- P& p/ l+ U( F$ q. k5 `+ l# s# C2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
) E) c6 e- x3 _6 N5 A5 |2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2 g8 n, G; v  J' g5 i# l2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
6 d$ G$ W2 ^0 [" L; c% ~! F4 `2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
: O' B' J  E; U  D* ~8 J2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
# ^; f& a/ `( Z/ {2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
- @' Z' Z; U% ovii
  Z6 a( S, N" N+ t1 u4 v2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
# t; [5 ]- u  V3 V" \1 c0 n& Y2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
, r6 q( B) h. e0 v; Pxi
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xxi
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
' Q: [  g$ s4 D$ S! h, _& @  `Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
CONTENTS
2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Principle of - ADC 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 _) [5 q6 Q% @; H3 U" C8 R9 {2 I" F3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
# o# x% Q4 M; _# V' v1 D" |2 L3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
; h, T0 |& w$ Z% Q* {8 `- Y3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 q: k+ |+ n% Z; _, q3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
6 X2 R3 i) l4 A( c3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
  {) N. x/ X4 B+ U5 N$ `3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
/ a2 ~! h7 j. g/ n. J" t1 }$ {3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
3.4.4 Performance Comparison of Traditional - Topologies . . 46
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2 `. }8 H' i, x4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
Level Approach 47
* i# c) r1 V* ^  O( f1 J) q0 \& @4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
$ R; `* q. o$ A. S' T5 o5 w: C; q/ ^2 h6 f4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
5 a; Y3 b: E  w5 G  A- ^( X4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
' ~$ Z3 V$ ~2 v) X! o4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
5 q" r+ s; d: X* u4 u4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
! ]* f+ [, M0 N- p# S" G  Z4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
  C! N% X+ T) m: v4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
6 A, W6 ?& e9 ~5 W: @6 m6 s  d  s4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
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, E, K3 g: ?  o8 O4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
) v3 K0 p- y; s& J. B3 c: f4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
5 J/ w* R( y8 }: f8 e+ S5 f4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
* W8 i. w7 b7 u2 O1 j4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
. P0 ^7 N5 ~$ I' T: W! I5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
$ z& l8 q" S& U7 Y. rCONTENTS ix
4 E, h0 V. i* w5 d) lCONTENTS
6 Conclusions 149
, o8 k; \( `, F: ~Bibliography 151
Index 157

scan7510

看不太懂
可能還沒學過吧
現在只能單純推一下
1 {5 @  C0 v+ f. v( Z. }謝大大分享

deltachen

謝謝大大的分享~知識因分享而壯大！

jjam

感覺是非常實用的內容
感謝大大的分享~~
) E! [1 x, {4 Y% |$ s1 G- i. [( [3 Z希望能對SDM有所認識與了解