Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
List of Tables
List of Figures
Symbols and Abbreviations
; K' ]& S* z, Y4 C# H% ePhysical
+ H) \+ d7 E( N3 _4 J1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 p& Y( Z6 ?# S1 M) r1 p1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ADCs in Nanometer CMOS Technologies 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
. v! l$ F. W: ?2 G2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
5 p  w/ `+ J5 P2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
" e$ L) r( u" p; B2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
/ U# T% o4 l3 A8 L- Y% v* A2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vii
2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
# v% i5 B# u4 j9 k# w2 G2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
& }: d1 |7 p+ {* g4 ~$ pxi
xiii
xxi
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
  h1 D) |# A/ d7 O% n5 I9 xDefinitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
  t0 D" B2 v. e! ^( rCONTENTS
- ~9 T& K/ R/ ?2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
( i) C% a& n! g1 f$ U& V2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9 t: A8 w. x) D( I; v. @3 Principle of - ADC 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 k* l- u0 B4 e* l6 ~9 ^9 Y3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
: Q9 c7 U0 p! Q; c; J3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
) ~( y$ F) R  n3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
7 K+ I9 G3 e: g4 g" d3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
! P5 `, a' k$ n! H3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
1 A4 P' r/ }/ K7 J2 d3.4.4 Performance Comparison of Traditional - Topologies . . 46
8 S3 U1 b; a1 L4 Z3 @$ L3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
: ^# T/ e+ q2 c, A7 s) e' Q4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
3 ]8 t% x- y; DLevel Approach 47
) T  ~# w3 N% u7 D& M0 c% W" }4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
; |6 b% U# V: E, r, q" l4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
: I) S( t7 [* t. y% G3 m4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
& l5 B6 _5 p' R9 V7 Q4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
9 d5 ?4 G8 I4 M; S8 k9 D6 W1 t4 lviii
' r  Z$ ?8 j. ^1 {. [( K4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
, l1 B# ?3 t" M* W  {4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
3 H; l7 x1 P  t. U- H; K4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
' w/ [- [4 c) k/ @4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
: `: k& D8 p$ V- ^' q! B4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
9 y4 ^' K0 I! A$ W' f7 k7 d4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
7 e& `8 X: g6 ?: T6 ^# s  g4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
, m, \/ L* K8 N4 C5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
! I. a7 b" M0 x- J) ECONTENTS ix
' _9 e/ o  k( L6 x: U5 ?3 \; F! ^4 LCONTENTS
6 Y) O+ J" h, j* v( D6 Conclusions 149
Bibliography 151
8 G' ^' I  F3 r/ X, \) LIndex 157

jjam

感覺是非常實用的內容
+ ]6 t  F  |/ }3 @) e感謝大大的分享~~
希望能對SDM有所認識與了解

deltachen

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scan7510

看不太懂
4 ]3 c& d5 E+ ]% q6 w可能還沒學過吧
現在只能單純推一下
謝大大分享