Calibration techniques in nyquist AD converters

cnasic

Table of contents
List of abbreviations
" v, G8 r0 M5 J$ O, R8 EList of symbols
Preface
1 Introduction 1
/ \2 O7 b$ D4 X6 Z% K1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
- S! E& [- }2 b/ F, J$ k0 Z) @1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Accuracy, speed and power relation 7
* Q. O( ?% a- Z  p. \0 W: _+ f2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
  [) k( u3 S! u& R2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2
0 v& ?7 h0 r& s2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
% z* O; Y1 c$ j/ g$ M2 ?( e0 y2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
! M; m6 k9 C0 P7 ?4 g# R$ C2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
# a) ?2 h0 a/ B8 B2.5 . . . . . . . . . . . . . . . . . . . . . 15
. R/ N) j0 J5 I: j8 |& _" ?/ w* a2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 A/D converter architecture comparison 21
% [+ f; q9 O8 Z: Y9 e" l" n) `3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
+ h: U$ Z" J5 w8 y3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
! |6 }5 z% ]) ?) O3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
' I1 L7 @4 C# a0 rThermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
( J% U& c3 W; l. E& KCMOS technology trends
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Table of contents
7 P1 N) w0 U! ?; b( V6 B3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
$ r$ v, |* l. k* [7 Z- ?  I3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
9 G# n, G. E9 [3 @0 x7 W/ A# |3 U3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
/ S+ Y% G( _  P: x5 n) {3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
4 g  u. \% l5 p" @# R& J3.7.2 Architecture comparison as a function of the resolution . . 57
, S  t8 k9 n' I# J3.7.3 Architecture comparison as a function of the sampling speed 65
3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 Enhancement techniques for two-step A/D converters 67
# L, L) A4 u$ v" X* R. F; [4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
/ {2 O+ A; L0 Y4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
! P/ p# A8 `4 q  }' L# s. b4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
, n8 ?; a; A1 m8 R8 l3 j4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2 W* r2 w' C4 K4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
/ S; G% j( R  F. T% O4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
" d" I/ e& Q* ]) }  ~1 M4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
# V% ~' n# W8 i- ]- y4.5.4 Offset extraction and analog compensation . . . . . . . . 91
, J; k4 g; d2 @9 u, s- ~% K  U4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 A 10-bit two-step ADC with analog online calibration 103
  m0 N5 d% `+ E9 R. P4 t5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
, P3 J  O1 b, C4 F' C$ F5.2
5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
# ]+ Z- e! q' }9 A; u1 @' ]5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
6 T( ~* ?9 J! O8 x2 l5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
- i0 {3 J) ]" d" E5 z1 w# d5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
+ M' I# Y* I8 W  U5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
: _( X+ f& y1 e; \6 {7 g5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
# l, r9 c5 F6 v5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
/ d# }; N3 S; n1 ^9 Q* B- n5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
: T4 h) {5 h: J7 j# d5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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$ C" ?4 R7 W$ h3 E8 c& m& nTwo-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
3 b- Q+ P3 E% H. \( c: z+ cTable of contents
8 _- Z( ~% m8 G% A5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
! d! \7 d6 k0 C7 q9 J7 A low-power 16-bit three-step ADC for imaging applications 149